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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
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- Vangal, Sriram (author)
- Linköpings universitet,Institutionen för systemteknik,Tekniska högskolan
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- Howard, Jason (author)
- Intel, Hilisboro, Oregon, USA
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- Ruhl, Gregory (author)
- Intel, Hilisboro, Oregon, USA
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- (creator_code:org_t)
- IEEE, 2007
- 2007
- English.
- In: IEEE International Solid-State Circuits Conference, San Fransisco, USA, 2007. - : IEEE. - 1424408539 ; , s. 98-99
- Conference paper (peer-reviewed)
Abstract
Subject headings
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- A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Keyword
- TECHNOLOGY
- TEKNIKVETENSKAP
Publication and Content Type
- ref (subject category)
- kon (subject category)
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- Howard, Jason
- Ruhl, Gregory
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- Iyer, Priya
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