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An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
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- Caputa, Peter (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
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- Svensson, Christer (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
- (creator_code:org_t)
- 2006
- 2006
- English.
- In: International Solid-State Circuits Conference 2006, San Fransisco, USA. - 1424400791
- Conference paper (other academic/artistic)
Abstract
Subject headings
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- A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.
Keyword
- CMOS integrated circuits
- delays
- integrated circuit design
- integrated circuit interconnections
- synchronisation
- 0.18 micron
- 5.4 mm
- CMOS process
- data synchronization
- data-clock skew
- global clock skew
- multicycle communication
- on-chip global wire delays
- synchronous latency-insensitive design
- TECHNOLOGY
- TEKNIKVETENSKAP
Publication and Content Type
- vet (subject category)
- kon (subject category)
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