On the specification and verification of VLSI systems

• System designers now have the opportunity to place on the order of 105-106 transistors on a single chip allowing larger and more complicated systems to be produced at reduced production costs. This opportunity increases the demand for appropriate design automation including tools for synthesis, analysis, and verification. However, human designers still are and will be our main source of innovation. In order to express and communicate new design ideas to a computer aided engineering environment some form of specification language is needed. Different tools and engineering situations put different requirements on a specification language. Is is important that all users of a language have a firm knowledge about how to interpret the language. This thesis proposes a specification language (ASL), a semantic model, and transformation rules related to the language. The thesis focuses upon the specification of a systems actional behaviour and the semantics provides a framework for the verification of a systems structural implementation versus its actional specification. A set of calculus, port and event reduction rules, and rules for port binding and partial evaluation are proposed as tools for verification.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)

Publication and Content Type

vet (subject category)

lic (subject category)