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Optimized Integrati...
Optimized Integration of Test Compression and Sharing for SOC Testing
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- Larsson, Anders, 1977- (author)
- Linköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system
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- Larsson, Erik, 1966- (author)
- Linköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system
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- Eles, Petru Ion, 1954- (author)
- Linköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system
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- Peng, Zebo, 1958- (author)
- Linköpings universitet,Tekniska högskolan,ESLAB - Laboratoriet för inbyggda system
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(creator_code:org_t)
- Nice, France : IEEE Computer Society Press, 2007
- 2007
- English.
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In: Design, Automation, and Test in Europe Conference DATE07,2007. - Nice, France : IEEE Computer Society Press. - 9783981080124 ; , s. 207-
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Abstract
Subject headings
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- The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Sciences (hsv//eng)
Keyword
- testing
- system-on-chip
- SOC
- test scheduling
- memory requirements
- test data compression
- constraint logic programming
- Computer science
- Datavetenskap
Publication and Content Type
- ref (subject category)
- kon (subject category)
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