An asynchronous architecture for modeling intersegmental neural communication

• This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented, data from this system are presented. © 2006 IEEE.

Keyword

Address event representation (AER)

Asynchronous circuits

Central pattern generator (CPG)

Neurobiological modeling

Neuromorphic engineering

Silicon neuron

VLSI architecture

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