Implementation of a bit-serial FFT processor with a hierarchical control structure

• A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high  performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a  hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented  as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

Electronics

Elektronik

Publication and Content Type

ref (subject category)

kon (subject category)