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Two-tone PLL for on...
Two-tone PLL for on-chip IP3 test
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- Ahmad, Shakeel, 1977- (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
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- Azizi, Kaveh (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
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- Esmaeil Zadeh, Iman (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
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- Dabrowski, Jerzy, 1952- (author)
- Linköpings universitet,Elektroniska komponenter,Tekniska högskolan
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(creator_code:org_t)
- IEEE, 2010
- 2010
- English.
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In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10). - : IEEE. - 9781424453085 ; , s. 3549-3552
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.
Keyword
- TECHNOLOGY
- TEKNIKVETENSKAP
Publication and Content Type
- ref (subject category)
- kon (subject category)
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