A study of the non-ideal properties of sample-and-hold circuits with respect to the analog bandwidth

• The fast evolving communication market demands decreased fabrication cost, which will be met by highly integrated circuit solutions. In the near future, we will see system-on-a-chip solutions in CMOS technology, where transceivers will be integrated on a single chip preferably, also with digital circuitry. Receiver topologies with A/D conversion at higher frequencies are interesting from an integration point of view. Therefore, a deeper understanding of the A/D converter limitations to cope with high-frequency signals is needed. This paper will highlight the track-and-hold circuit linearity, which is a frequency dependent fundamental limit on the A/D conversion accuracy

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