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Buffer-Aware Analys...
Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
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- Liu, Meng (author)
- Mälardalens högskola,Inbyggda system
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- Becker, Matthias (author)
- Mälardalens högskola,Inbyggda system
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- Behnam, Moris (author)
- Mälardalens högskola,Inbyggda system
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- Nolte, Thomas (author)
- Mälardalens högskola,Inbyggda system
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(creator_code:org_t)
- 2017
- 2017
- English.
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In: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017. - 9781509060580 ; , s. 567-575
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- Network-on-Chip (NoC) is a communication sub-system which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)
Keyword
- Many-CoreNetwork-on-ChipBufferTiming Analysis
Publication and Content Type
- ref (subject category)
- kon (subject category)
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