Optimization of memory allocation for real-time video processing on FPGA

• We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)

NATURVETENSKAP  -- Matematik (hsv//swe)

NATURAL SCIENCES  -- Mathematics (hsv//eng)

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

Computer science

Computer science

Datavetenskap

MATHEMATICS

MATEMATIK

Electrical engineering, electronics and photonics

Elektroteknik, elektronik och fotonik

Publication and Content Type

ref (subject category)

kon (subject category)