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Growth of SiGe laye...
Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)
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- Wang, Guilei (author)
- Chinese Academy of Sciences, Beijing, China
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- Kolahdouz, M. (author)
- University of Tehran, Tehran, Iran
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- Luo, Jun (author)
- Chinese Academy of Sciences, Beijing, China
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- Qin, Changliang (author)
- Chinese Academy of Sciences, Beijing, China
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- Gu, Shihai (author)
- Chinese Academy of Sciences, Beijing, China
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- Kong, Zhenzhen (author)
- Chinese Academy of Sciences, Beijing, China
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- Yin, Xiaogen (author)
- Chinese Academy of Sciences, Beijing, China
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- Xiong, Wenjuan (author)
- Chinese Academy of Sciences, Beijing, China
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- Zhao, Xuewei (author)
- Chinese Academy of Sciences, Beijing, China
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- Liu, Jinbiao (author)
- Chinese Academy of Sciences, Beijing, China
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- Yang, Tao (author)
- Chinese Academy of Sciences, Beijing, China
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- Li, Junfeng (author)
- Chinese Academy of Sciences, Beijing, China
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- Yin, Huaxiang (author)
- Chinese Academy of Sciences, Beijing, China
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- Zhu, Huilong (author)
- Chinese Academy of Sciences, Beijing, China
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- Wang, Wenwu (author)
- Chinese Academy of Sciences, Beijing, China
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- Zhao, Chao (author)
- Chinese Academy of Sciences, Beijing, China
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- Ye, Tianchun (author)
- Chinese Academy of Sciences, Beijing, China
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- Radamson, Henry H. (author)
- Mittuniversitetet,Institutionen för elektronikkonstruktion,Chinese Academy of Sciences, Beijing, China
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(creator_code:org_t)
- 2019-01-17
- 2020
- English.
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In: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 26-33
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Abstract
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- In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publication and Content Type
- ref (subject category)
- art (subject category)
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- By the author/editor
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Wang, Guilei
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Kolahdouz, M.
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Luo, Jun
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Qin, Changliang
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Gu, Shihai
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Kong, Zhenzhen
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show more...
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Yin, Xiaogen
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Xiong, Wenjuan
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Zhao, Xuewei
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Liu, Jinbiao
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Yang, Tao
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Li, Junfeng
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Yin, Huaxiang
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Zhu, Huilong
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Wang, Wenwu
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Zhao, Chao
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Ye, Tianchun
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Radamson, Henry ...
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show less...
- About the subject
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- ENGINEERING AND TECHNOLOGY
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ENGINEERING AND ...
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and Electrical Engin ...
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and Other Electrical ...
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Mid Sweden University