Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure

• For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

Low power

Digital CMOS

Floating-gate

Electrical engineering, electronics and photonics

Elektroteknik, elektronik och fotonik

Publication and Content Type

ref (subject category)

kon (subject category)