Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application

• Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure. © 2020, The Author(s).

Keyword

Auto-doping

Dopant segregation

Phosphorus-doped silicon

RPCVD

Selective etch

SiGe

Chlorine compounds

Dry etching

Field effect transistors

Germanium

Multilayers

Phosphorus

Si-Ge alloys

Silanes

Silicon

Wet etching

Integrated circuit manufacturing

Lateral directions

Phosphorus-doped

Selective etching

Technology nodes

Vertical etching

Vertical transistors

Wet and dry etchings

Phosphorus compounds

Publication and Content Type

ref (subject category)

art (subject category)