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D-latch for Subthre...
D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
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- Alfredsson, Jon (author)
- Mittuniversitetet,Institutionen för informationsteknologi och medier (-2013),Electronics design division
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- Aunet, Snorre (author)
- Department of Informatics, University of Oslo
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(creator_code:org_t)
- IEEE conference proceedings, 2007
- 2007
- English.
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In: 2007 NORCHIP. - : IEEE conference proceedings. - 9781424415168 ; , s. 146-149
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Abstract
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- When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- Subthreshold
- Floating-gate
- digital
- latch
- low power
- Electrical engineering, electronics and photonics
- Elektroteknik, elektronik och fotonik
Publication and Content Type
- ref (subject category)
- kon (subject category)
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