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Performance of CMOS...
Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply
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- Alfredsson, Jon (författare)
- Mittuniversitetet,Institutionen för informationsteknologi och medier (-2013),Electronics design division
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- Aunet, Snorre (författare)
- Department of Informatics, University of Oslo
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(creator_code:org_t)
- Berlin : Springer, 2007
- 2007
- Engelska.
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Ingår i: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation. - Berlin : Springer. - 9783540744412 ; , s. 536-546
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Abstract
Ämnesord
Stäng
- To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- low power
- Electrical engineering, electronics and photonics
- Elektroteknik, elektronik och fotonik
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
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