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Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations
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- Alfredsson, Jon (author)
- Mittuniversitetet,Institutionen för informationsteknologi och medier (-2013),Electronics design division
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- Aunet, Snorre (author)
- Department of Informatics, University of Oslo
- (creator_code:org_t)
- 2008
- 2008
- English.
- In: Proceedings of IFIP VLSI-SOC Conference 2008.
- Conference paper (peer-reviewed)
Abstract
Subject headings
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- The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- low power
- digital CMOS
- subthreshold
- floating-gate design
- Electrical engineering, electronics and photonics
- Elektroteknik, elektronik och fotonik
Publication and Content Type
- ref (subject category)
- kon (subject category)
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