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Bounding Loop Iterations for Timing Analysis
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- Christopher Healy, Mikael Sjödin, Viresh Rustagi and David Whalley (author)
- Uppsala universitet,Institutionen för informationsteknologi
- (creator_code:org_t)
- 1998
- 1998
- English.
- In: IEEE Real-Time Applications Symposium; RTAS'98.
- Conference paper (peer-reviewed)
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Keyword
- WCET, Static Analysis, Real-time systems
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- ref (subject category)
- kon (subject category)
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