Speculative inter-thread store-to-load forwarding in SMT architectures

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Feliu, JosueUniv Murcia, Comp Engn Dept, Murcia 30100, Spain. (author)

Speculative inter-thread store-to-load forwarding in SMT architectures

Article/chapterEnglish2023

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Elsevier,2023
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LIBRIS-ID:oai:DiVA.org:uu-492103
https://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-492103URI
https://doi.org/10.1016/j.jpdc.2022.11.007DOI

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Language:English
Summary in:English

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Applications running on out-of-order cores have benefited for decades of store-to-load forwarding which accelerates communication of store values to loads of the same thread. Despite threads running on a simultaneous multithreading (SMT) core could also access the load queues (LQ) and store queues (SQ) / store buffers (SB) of other threads to allow inter-thread store-to-load forwarding, we have skipped exploiting it because if we allow communication of different SMT threads via their LQs and SQs/SBs, write atomicity may be violated with respect to the outside world beyond the acceptable model of read -own-write-early multiple-copy atomicity (rMCA).In our prior work, we leveraged this idea to propose inter-thread store-to-load forwarding (ITSLF). ITLSF accelerates synchronization and communication of threads running in a simultaneous multi-threading processor by allowing stores in the store-queue of a thread to forward data to loads of another thread running in the same core without violating rMCA.In this work, we extend the original ITSLF mechanism to allow inter-thread forwarding from speculative stores (Spec-ITSLF). Spec-ITSLF allows forwarding store values to other threads earlier, which further accelerates synchronization. Spec-ITSLF outperforms a baseline SMT core by 15%, which is 2% better on average (and up to 5% for the TATP workload) than the original ITSLF mechanism. More importantly, Spec-ITSLF is on par with the original ITSLF mechanism regarding storage overhead but does not need to keep track of the speculative state of stores, which was an important source of overhead and complexity in the original mechanism. (c) 2022 The Author(s). Published by Elsevier Inc. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Subject headings and genre

NATURVETENSKAP Data- och informationsvetenskap Datavetenskap hsv//swe
NATURAL SCIENCES Computer and Information Sciences Computer Sciences hsv//eng
NATURVETENSKAP Data- och informationsvetenskap Datorteknik hsv//swe
NATURAL SCIENCES Computer and Information Sciences Computer Engineering hsv//eng
Simultaneous multithreading
Memory consistency
Store -to -load forwarding
Multiple -copy atomicity

Added entries (persons, corporate bodies, meetings, titles ...)

Ros, AlbertoUniv Murcia, Comp Engn Dept, Murcia 30100, Spain. (author)
Acacio, Manuel E.Univ Murcia, Comp Engn Dept, Murcia 30100, Spain. (author)
Kaxiras, StefanosUppsala universitet,Datorarkitektur och datorkommunikation,Avdelningen för datorteknik,Uppsala Univ, Dept Informat Technol, S-75236 Uppsala, Sweden.(Swepub:uu)steka984 (author)
Univ Murcia, Comp Engn Dept, Murcia 30100, Spain.Datorarkitektur och datorkommunikation (creator_code:org_t)

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In:Journal of Parallel and Distributed Computing: Elsevier173, s. 94-1060743-73151096-0848

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