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Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations

Jose Gomez-Hernandez, Eduardo (author)
Univ Murcia, Dept Comp Engn, Murcia, Spain.
Cebrian, Juan M. (author)
Univ Murcia, Dept Comp Engn, Murcia, Spain.
Titos-Gil, Ruben (author)
Univ Murcia, Dept Comp Engn, Murcia, Spain.
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Kaxiras, Stefanos (author)
Uppsala universitet,Datorarkitektur och datorkommunikation,Avdelningen för datorteknik,Datorteknik
Ros, Alberto (author)
Univ Murcia, Dept Comp Engn, Murcia, Spain.
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Univ Murcia, Dept Comp Engn, Murcia, Spain Datorarkitektur och datorkommunikation (creator_code:org_t)
2021-10-17
2021
English.
In: Proceedings of 54th Annual IEEE/ACM International Symposium on Microarchitecture, Micro 2021. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450385572 ; , s. 337-349
  • Conference paper (peer-reviewed)
Abstract Subject headings
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  • Critical sections that read, modify, and write (RMW) a small set of addresses are common in parallel applications and concurrent data structures. However, to escape from the intricacies of finegrained locks, which require reasoning about all possible thread interleavings, programmers often resort to coarse-grained locks to ensure atomicity. This results in atomic protection of a much larger set of potentially conflicting addresses, and, consequently, increased lock contention and unneeded serialization. As many before us have observed, these problems would be solved if only general RMW multi-address atomic operations were available, but current proposals are impractical because of deadlock scenarios that appear due to resource limitations. Alternatively, transactional memory can detect conflicts at run-time aiming to maximize concurrency, but it has significant overheads in highly-contended critical sections. In this work, we propose multi-address atomic operations (MAD atomics). MADatomics achieve complexity-effective, non-speculative, non-deadlocking, fine-grained locking for multiple addresses, relying solely on the coherence protocol and a predetermined locking order. Unlike prior works, MAD atomics address the challenge of enabling atomic modification over a set of cachelines with arbitrary addresses, simultaneously locking all of them while sidestepping deadlock. MAD atomics only require a small storage per core (around 68 bytes), while significantly outperforming typical lock implementations. Indeed, our evaluation using gem5-20 shows that MAD atomics can improve performance by up to 18x (3.4x, on average, for the applications and concurrent data structures evaluated in this work) over a baseline implemented with locks running on 16 cores. More importantly, the improvement still reaches 2.7x, on average, compared to an Intel hardware transactional memory implementation running on 16 cores.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)
NATURVETENSKAP  -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)

Keyword

Multi-core architectures
synchronization
critical sections
atomicity
multi-address atomics

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ref (subject category)
kon (subject category)

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