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Fully Integrated Ra...
Fully Integrated Radio over Fiber Downlink for Distributed Multi-antenna Systems in 65nm CMOS
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- Ahmad, Waqas (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Nejdel, Anders (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Törmänen, Markus (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Sjöland, Henrik (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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(creator_code:org_t)
- 2014
- 2014
- English.
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In: 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). - 9781479978694 ; , s. 353-356
- Related links:
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http://dx.doi.org/10...
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https://doi.org/10.1...
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Abstract
Subject headings
Close
- This paper presents a fully integrated downlink for low-cost remote antenna units in fiber-fed distributed multi-antenna systems. To reduce the cost of optical parts, an intermediate frequency(IF) signal is distributed over the fiber, and the circuit consists of an optical receiver, a single side-band frequency up-converting radio transmitter, and LO generation circuitry. The optical to electrical conversion gain(V/W) of the system is 59dB, and an output referred 1dB compression point of +6dBm and an OIP3 of +17dBm are measured. The SFDR of the circuit is 96.5 dBHz^2/3. The phase noise of the PLL measured at 4.2GHz is -145dBc/Hz at 20MHz offset, where as the reference spur level is -58dBc. The circuit is fabricated in a standard 65nm CMOS process and occupies just 0.8mm^2 of chip area including bond pads.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publication and Content Type
- kon (subject category)
- ref (subject category)
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