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A 5GHz 90-nm CMOS a...
A 5GHz 90-nm CMOS all digital phase-locked loop
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- Lu, Ping (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Sjöland, Henrik (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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(creator_code:org_t)
- 2010-07-07
- 2011
- English.
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In: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 66:1, s. 49-59
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Abstract
Subject headings
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- An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- RF
- Digitally Controlled Oscillator (DCO)
- Phase Locked Loop (PLL)
- Time-to-Digital Converter (TDC)
- All Digital Phase-Locked Loop (ADPLL)
- CMOS
Publication and Content Type
- art (subject category)
- ref (subject category)
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