A New Digital Front-End for Flexible Reception in Software Defined Radio

Diaz, Isael (author)

Zhang, Chenxin (author)

Hollevoet, Lieven (author)

Svensson, Jim (author)

Rodrigues, Joachim (author): Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH

Wilhelmsson, Leif (author)

Olsson, Thomas (author)

Van der Perre, Liesbet (author)

Öwall, Viktor (author): Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH

(creator_code:org_t)

Elsevier BV, 2015
2015
English.
In: Microprocessors and Microsystems. - : Elsevier BV. - 0141-9331. ; 39:8, s. 889-900

Related links:: http://dx.doi.org/10...; show more...; https://lup.lub.lu.s...; https://doi.org/10.1...; show less...

Abstract Subject headings

Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still remains in the Digital Front-End (DFE), where many operations are too complex or energy hungry to be implemented as software instructions. Thus, new architectures are needed to feed the SDR digital baseband while keeping complexity and energy consumption at bay. In this article the architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals is presented. The flexibility needed for multi-standard support is demonstrated by detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. Moreover, the proposed architecture has been fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5 mm2. The core module of the DFE-Rx, the synchronization engine, has been measured at 1.2 V and reports an average power consumption of 1.9 mW during Wireless Local Area Network (WLAN) reception and 1.6 mW during configuration, while running at 10 MHz.

By the author/editor: Diaz, Isael; Zhang, Chenxin; Hollevoet, Lieve ...; Svensson, Jim; Rodrigues, Joach ...; Wilhelmsson, Lei ...; show more...; Olsson, Thomas; Van der Perre, L ...; Öwall, Viktor; show less...

About the subject

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