Low power analog channel decoder in sub-threshold 65nm CMOS

• This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI’s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

sub-threshold CMOS

integrated circuits

low power circuits

Decoders

Publication and Content Type

kon (subject category)

vet (subject category)