A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

• Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

energy dissipation

measurements

sub-threshold

half band digital (HBD) filters

65 nm CMOS

and architectures.

Publication and Content Type

kon (subject category)

ref (subject category)