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A programmable 16-l...
A programmable 16-lane SIMD ASIP for massive MIMO
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- Malkowsky, Steffen (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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- Prabhu, Hemanth (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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- Liu, Liang (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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- Edfors, Ove (author)
- Lund University,Lunds universitet,Kommunikationsteknologi,Forskargrupper vid Lunds universitet,Communications Engineering,Lund University Research Groups
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- Öwall, Viktor (author)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,Integrated Electronic Systems,Lund University Research Groups
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(creator_code:org_t)
- 2019
- 2019
- English.
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In: 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. - 9781728103976 ; 2019
- Related links:
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http://dx.doi.org/10...
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https://doi.org/10.1...
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Abstract
Subject headings
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- This paper presents a 16-lane, 16-bit complex application-specific instruction processor (ASIP) for baseband processing in massive multiple-input multiple-output (MIMO). The architecture utilizes a 3/4-way very large instruction word (VLIW) with highly efficient pre- and post-processing units specifically trimmed for massive MIMO requirements. Architecture optimizations include features like single cycle vector-dot-product, vector indexing and broadcasting, hardware loops and full complex accumulator to provide high performance for various massive MIMO algorithms. Moreover, the ASIP is fully C-programmable, which is crucial for adapting to the evolving 5G standard. In our evaluation, a full massive MIMO up-link detection is executed in ≈11k clock cycles while synthesis results in ST 28 nm FD-SOI suggest a clock frequency of 900 MHz equating in a detection throughput of 330 Mb/s for a 128×16 massive MIMO system.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Kommunikationssystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Communication Systems (hsv//eng)
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