Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

• We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.

Subject headings

NATURVETENSKAP  -- Fysik -- Den kondenserade materiens fysik (hsv//swe)

NATURAL SCIENCES  -- Physical Sciences -- Condensed Matter Physics (hsv//eng)

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

nanowires (NWs)

Field-effect transistor (FET)

InAs

on Si

III-V

wrap gate

Publication and Content Type

art (subject category)

ref (subject category)