A Digital Baseband for Low Power FSK Based Receiver in 65 nm CMOS

• The design of a digital baseband for a low power wireless receiver in 65 nm CMOS is presented. It consists of decimation filtering, matched filters for data detection, and preamble based synchronization. The circuit was designed using low threshold devices in both low power (LP-LVT) and general-purpose (GP-LVT) domains. The fabricated circuits were functionally verified, and silicon measurements show a minimum energy dissipation of around 454 pJ and 708 pJ per output bit at a rate of 500 kbit/s for the LP-LVT and GP-LVT implementations, respectively.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

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