Dynamic Equalizer Power Dissipation Optimization

• We investigate power dissipation/performance trade-off in a 28nm ASIC implementation of a parallel dynamic equalizer. Over 50% dissipation improvement is possible by sample pruning during filter updates, with only minor tracking-performance reduction.

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TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

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