Hysteresis modeling in graphene field effect transistors

• Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage nu(g) versus the drain current i(d) reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Annan teknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Other Engineering and Technologies (hsv//eng)

TEKNIK OCH TEKNOLOGIER  -- Nanoteknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Nano-technology (hsv//eng)

Publication and Content Type

art (subject category)

ref (subject category)