Search: onr:"swepub:oai:research.chalmers.se:a9a25bf0-381e-4b23-b4b7-7529cfbd90de" >
Towards a Performan...
Towards a Performance- and Energy-Efficient Data Filter Cache
-
- Bardizbanyan, Alen, 1986 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
-
- Själander, Magnus, 1977 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
-
- Whalley, David (author)
- Florida State University
-
show more...
-
- Larsson-Edefors, Per, 1967 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
-
show less...
-
(creator_code:org_t)
- ISBN 9781450319058
- 2013-02-24
- 2013
- English.
-
In: Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27. - New York, NY, USA : ACM. - 9781450319058 ; , s. 21-28
- Related links:
-
http://publications.... (primary) (free)
-
show more...
-
http://www.cs.fsu.ed...
-
https://research.cha...
-
https://doi.org/10.1...
-
show less...
Abstract
Subject headings
Close
- As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedded processor's total power dissipation, techniques that decrease L1 DC accesses can significantly enhance processor energy efficiency. Filter caches are known to efficiently decrease the number of accesses to instruction caches. However, due to the irregular access pattern of data accesses, a conventional data filter cache (DFC) has a high miss rate, which degrades processor performance. We propose to integrate a DFC with a fast address calculation technique to significantly reduce the impact of misses and to improve performance by enabling one-cycle loads. Furthermore, we show that DFC stalls can be eliminated even after unsuccessful fast address calculations, by simultaneously accessing the DFC and L1 DC on the following cycle. We quantitatively evaluate different DFC configurations, with and without the fast address calculation technique, using different write allocation policies, and qualitatively describe their impact on energy efficiency. The proposed design provides an efficient DFC that yields both energy and performance improvements.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)
Keyword
- Data cache
- Execution time
- Speculation
- Energy
- Memory hierarchy
Publication and Content Type
- kon (subject category)
- ref (subject category)
Find in a library
To the university's database