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3D chip stacking us...
3D chip stacking using planarized carbon nanotubes as through-silicon-vias
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- Jeppson, Kjell, 1947 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Wang, Teng, 1983 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Liu, Johan, 1960 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Larsson-Edefors, Per, 1967 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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(creator_code:org_t)
- 2009
- 2009
- English.
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In: Swedish System on Chip Conference.
- Related links:
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https://research.cha...
Abstract
Subject headings
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- Future miniaturization of advanced electronic systems will require 3D chip-to-chip stacking of high performance processor chips. Such systems raise a number of questions concerning power distribution and thermal management issues. Efficient through-silicon-via (TSV) technology and new thermal interface materials will be required for such systems to be successful. Carbon nanotubes (CNT) have been suggested as a candidate material with good mechanical properties, and good thermal and electrical conductivities superior to those of copper TSVs. In this paper we will describe our efforts on producing through-silicon-vias based on carbon nanotube bundles grown from the bottom of 150 m deep silicon vias with 50*50 µm openings. The resistances of such CNT vias have been electrically measured and found to be about 2.0 kΩ, a result very close to previously reported values. However, these values are orders of magnitude too high for practical use and not at all close to values reported from measurements on short carbon nanotubes. New processes are suggested too improve growth of long CNTs.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publication and Content Type
- kon (subject category)
- vet (subject category)
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