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Early results from ...
Early results from ERA embedded reconfigurable architectures
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- Wong, S. (author)
- Technische Universiteit Delft,Delft University of Technology (TU Delft)
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- Brandon, Anthony (author)
- Technische Universiteit Delft,Delft University of Technology (TU Delft)
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- Anjam, F. (author)
- Technische Universiteit Delft,Delft University of Technology (TU Delft)
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- Seedorf, R. (author)
- Technische Universiteit Delft,Delft University of Technology (TU Delft)
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- Giorgi, R. (author)
- Università degli Studi di Siena,University of Siena
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- Yu, Z. (author)
- Università degli Studi di Siena,University of Siena
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- Puzovic, N. (author)
- Università degli Studi di Siena,University of Siena
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- McKee, Sally A, 1963 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Själander, Magnus, 1977 (author)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Carro, L. (author)
- Universidade Federal do Rio Grande do Sul (UFRGS)
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- Keramidas, G. (author)
- Industrial Systems Institute
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(creator_code:org_t)
- ISBN 9781457704345
- 2011
- 2011
- English.
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In: 9th IEEE International Conference on Industrial Informatics, INDIN 2011, Lisbon, 26-29 July 2011. - 1935-4576. - 9781457704345 ; , s. 816-822
- Related links:
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http://dx.doi.org/10...
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https://doi.org/10.1...
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Abstract
Subject headings
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- The growing complexity and diversity of embedded systems combined with continuing demands for higher performance and lower power consumption place increasing pressure on embedded platforms designers. To address these problems, the Embedded Reconfigurable Architectures project (ERA), investigates innovations in both hardware and tools to create next-generation embedded systems. Leveraging adaptive hardware enables maximum performance for given power budgets. We design our platform via a structured approach that allows integration of reconfigurable computing elements, network fabrics, and memory hierarchy components. Commercially available, off-the-shelf processors are combined with other proprietary and application-specific, dedicated cores. These computing and network elements can adapt their composition, organization, and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given application(s). Likewise, network elements and topologies and memory hierarchy organization can be selected both statically at design time and dynamically at run-time. Hardware details are exposed to the operating system, run-time system, compiler, and applications. This combination supports fast platform prototyping of high-efficient embedded system designs. Our design philosophy supports the freedom to flexibly tune all these hardware elements, enabling a better choice of power/performance trade-offs than that afforded by the current state of the art.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences (hsv//eng)
Keyword
- adaptive embedded platform
- VEX VLIW processor
- benchmarking
Publication and Content Type
- kon (subject category)
- ref (subject category)
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- By the author/editor
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Wong, S.
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Brandon, Anthony
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Anjam, F.
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Seedorf, R.
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Giorgi, R.
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Yu, Z.
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show more...
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Puzovic, N.
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McKee, Sally A, ...
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Själander, Magnu ...
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Carro, L.
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Keramidas, G.
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show less...
- About the subject
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- NATURAL SCIENCES
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NATURAL SCIENCES
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and Computer and Inf ...
- Articles in the publication
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9th IEEE Interna ...
- By the university
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Chalmers University of Technology