Camera and LCM IP-Cores for NIOS SOPC System

QC 20120217
This paper presents the development of IP-Cores to integrate the Terasic DC2 Camera and LCM (LCD Module) daughter boards into an Altera Nios System, so that the image can be further processed by embedded software or custom hardware instructions. Among other challenges overcome during this work are clock-domain crossing, synchronizing FIFO design, variable and pipelined burst control, multi-masters contention for system memory and image frame buffer switching. In addition, we designed software device drivers, and API functions intended for graphics, image processing and video control; which are part of the IP deliverables. In a brief, this work describes some concepts and methodologies involved in the creation of IP-Cores for an Altera SOPC; it also presents the results of the designed CAM-IP and LCM-IP Cores working in an application demo, which constitutes a real solution and a reference design.

Sander, Ingo,1964-KTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1l8osh2 (författare)
Öberg, JohnnyKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1t0l5al (författare)
KTHElektronik- och datorsystem, ECS (creator_code:org_t)

Ingår i:6th FPGAworld Conference, Academic Proceedings 2009New York : ACM, s. 18-239781605588797

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