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An Application Spec...
An Application Specific Vector Processor for Efficient Massive MIMO Processing
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- Attari, Mohammad (författare)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,LTH profilområde: AI och digitalisering,LTH profilområden,Lunds Tekniska Högskola,Integrated Electronic Systems,Lund University Research Groups,LTH Profile Area: AI and Digitalization,LTH Profile areas,Faculty of Engineering, LTH
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- Ferreira, Lucas (författare)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,LTH profilområde: AI och digitalisering,LTH profilområden,Lunds Tekniska Högskola,Integrated Electronic Systems,Lund University Research Groups,LTH Profile Area: AI and Digitalization,LTH Profile areas,Faculty of Engineering, LTH
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- Liu, Liang (författare)
- Lund University,Lunds universitet,System på chips (master),Utbildningsprogram, LTH,Lunds Tekniska Högskola,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,LTH profilområde: Nanovetenskap och halvledarteknologi,LTH profilområden,LTH profilområde: AI och digitalisering,Embedded Electronics Engineering (M.Sc.),Educational programmes, LTH,Faculty of Engineering, LTH,Integrated Electronic Systems,Lund University Research Groups,LTH Profile Area: Nanoscience and Semiconductor Technology,LTH Profile areas,Faculty of Engineering, LTH,LTH Profile Area: AI and Digitalization,Faculty of Engineering, LTH
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- Malkowsky, Steffen (författare)
- Lund University,Lunds universitet,Integrerade elektroniksystem,Forskargrupper vid Lunds universitet,LTH profilområde: Nanovetenskap och halvledarteknologi,LTH profilområden,Lunds Tekniska Högskola,LTH profilområde: AI och digitalisering,Integrated Electronic Systems,Lund University Research Groups,LTH Profile Area: Nanoscience and Semiconductor Technology,LTH Profile areas,Faculty of Engineering, LTH,LTH Profile Area: AI and Digitalization,Faculty of Engineering, LTH
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(creator_code:org_t)
- 2022
- 2022
- Engelska 12 s.
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; , s. 1-12
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- This paper presents an implementation for a baseband massive multiple-input multiple-output (MIMO) application-specific instruction set processor (ASIP). The ASIP is geared with vector processing capabilities in the form of single instruction multiple data (SIMD), and furthermore exploits instruction level parallelism by employing a very large instruction word (VLIW) architecture. Additionally, a systolic array is built into the pipeline which is tuned to speed up matrix calculations. A parallel memory subsystem and stand-alone accelerators are integrated into the ASIP architecture in order to meet the processing requirement. The processor is synthesized in 22FD-SOI technology running at a clock frequency of 800 . The system achieves a maximum detection throughput of 0.75 Gb/s/mm $^2$ for a $128\times 8$ massive MIMO system.
Ämnesord
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Nyckelord
- 5G
- accelerator architecture
- ASIP
- Baseband
- baseband processor
- communications processor
- Complexity theory
- Computer architecture
- computer architecture
- Massive MIMO
- massive MIMO
- Mathematical models
- Matrix decomposition
- matrix processor
- parallel memory
- Precoding
- programmable processor
- SIMD
- systolic arrays
- vector processor
- VLIW
Publikations- och innehållstyp
- art (ämneskategori)
- ref (ämneskategori)
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