| 1. |
- Blad, Anton, 1981-, et al.
(författare)
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A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences
- 2006
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Ingår i: Asia Pacific Conference on Circuits and Systems,2006. - : IEEE.
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Konferensbidrag (refereegranskat)abstract
- A formulation based on multirate theory is introduced for analog-to-digital converters using parallel sigma-delta modulators in conjunction with modulation sequences. It is shown how the formulation can be used to analyze a system's sensitivity to channel mismatch errors by means of circulant and pseudo-circulant matrices. It is demonstrated how the time-interleaved-modulated (TIM), Hadamard-modulated (HM) and frequency-band decomposition (FBD) converters can be viewed as special cases of this more general description, and it is shown why the TIM and HM ADCs are sensitive to channel mismatch errors, whereas the FBD ADCs are not.
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| 2. |
- Blad, Anton, 1981-, et al.
(författare)
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A Hybrid Early Decision-Probability Propagation Decoding Algorithm for Low-Density Parity-Check Codes
- 2005
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Ingår i: Asilomar Conference on Signals, Systems and Computers,2005. - : IEEE. ; , s. 586-
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Konferensbidrag (refereegranskat)abstract
- Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate the performance of a hybrid decoding algorithm, using an approximating early decision algorithm and a regular probability propagation algorithm. When the early decision algorithm fails, the block is re-decoded using a probability propagation decoder. As almost all errors are detectable, the error correction performance of the hybrid algorithm is negligibly detoriated. However, simulations still achieve a 32% decrease of memory accesses.
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| 3. |
- Blad, Anton, 1981-, et al.
(författare)
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An early decision decoding algorithm for LDPC codes using dynamic thresholds
- 2005
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Ingår i: European Conference on Circuit Theory and Design,2005. - : IEEE. ; , s. III/285-
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Konferensbidrag (refereegranskat)abstract
- Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. This reduces the amount of messages passed by the algorithm, which can be expected to reduce the switching activity of a hardware implementation. While direct application of the modification results in severe performance penalties, we show how to adapt the algorithm to reduce the impact, resulting in a negligible decrease in error correction performance.
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| 4. |
- Blad, Anton, 1981-, et al.
(författare)
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An LDPC decoding algorithm utilizing early decisions
- 2005
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Ingår i: National Conference of Radio Science RVK,2005.
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Konferensbidrag (refereegranskat)abstract
- We investigate a modification to the sum-product algorithm used for decoding low-density parity-check (LDPC) codes. The sum-product algorithm is algorithmically simple and highly parallelizable, but suffers from high memory usage, making LDPC codes unsuitable for usage in battery powered devices such as cell phones and PDAs. The proposed modification defines a measure of bit reliabilities during the decoding process. Whenever the reliability of a bit is over a certain threshold, the bit is declared decided, and its messages are no longer calculated. We give experimental results for white Gaussian channels, and show that the amount of memory accesses can be substantially reduced, while performance does not suffer significantly. At a bit error rate of 10^-4, the number of memory accesses is halved, while the required transmitter power increases about 0.3 dB.
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| 5. |
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| 6. |
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| 7. |
- Blad, Anton, 1981-, et al.
(författare)
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Design Trade-Offs for Linear-Phase FIR Decimation Filters and SD-Modulat ors
- 2006
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Ingår i: 14th European Signal Processing Conference,2006. - Wien, Austria : EURASIP.
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Konferensbidrag (refereegranskat)abstract
- In this paper we examine the relation between signal-to-noise-ratio, oversampling ratio, transition bandwidth, and filter order for some commonly used sigma-delta-modulators and corresponding decimation filters. The decimation filters are equi-ripple finite impulse response filters and it is demonstrated that, for any given filter order, there exists an optimum choice of the stopband ripple and stopband edge which minimizes the signal-to-noise-ratio degradation.
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| 8. |
- Blad, Anton, 1981-, et al.
(författare)
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Early decision decoding methods for low-density parity-check codes
- 2005
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Ingår i: Swedish System-on-Chip Conference,2005.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. Currently, there are two early decision schemes proposed. We compare their theoretical performances and their suitability for hardware implementation. We also propose a new decision method, which we call weak decisions, that offers an increase in performance by a factor of two.
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| 9. |
- Blad, Anton, 1981-
(författare)
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Early-Decision Decoding of LDPC Codes
- 2009
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, withuncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.In this thesis, a modification to the sum-product decoding algorithm called early-decision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sum-product decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization andenergy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.
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| 10. |
- Blad, Anton, 1981-, et al.
(författare)
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Energy-Efficient Data Representation in LDPC Decoders
- 2006
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 42:18, s. 1051-1052
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Tidskriftsartikel (refereegranskat)abstract
- Data representations for LDPC decoders using the sum-product algorithm in the log-likelihood domain are considered. It is suggested that the look-up table implementation of the domain transform function is separated into two parts, allowing a compact representation of the internal state data. Memories and bus widths can be reduced by typically 16\%, while the imposed hardware overhead is insignificant.
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