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Sökning: WFRF:(Llosa Josep)

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1.
  • Qasem, Apan, et al. (författare)
  • Lightning Talks of EduHPC 2022
  • 2022
  • Ingår i: 2022 IEEE/ACM INTERNATIONAL WORKSHOP ON EDUCATION FOR HIGH PERFORMANCE COMPUTING (EDUHPC). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 42-49
  • Konferensbidrag (refereegranskat)abstract
    • The lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of topics in broadening PDC education: (i) curriculum development efforts for the European Masters in HPC program, (ii) bootcamps for CI professionals who support the running of AI workloads on HPC systems, (iii) a GPU programming course following the Carpentries model and (iv) peer-review assignments to help students write efficient parallel algorithms within sustainable software libraries.
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2.
  • Vera, Xavier, et al. (författare)
  • An accurate cost model for guiding data locality transformations
  • 2005
  • Ingår i: ACM Transactions on Programming Languages and Systems. - : Association for Computing Machinery (ACM). - 0164-0925 .- 1558-4593. ; 27:5, s. 946-987
  • Tidskriftsartikel (refereegranskat)abstract
    • Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs exhibit sufficient data locality. The performance of the memory hierarchy can be improved by means of data and loop transformations. Tiling is a loop transformation that aims at reducing capacity misses by shortening the reuse distance. Padding is a data layout transformation targeted to reduce conflict misses. This article presents an accurate cost model that describes misses across different hierarchy levels and considers the effects of other hardware components such as branch predictors. The cost model drives the application of tiling and padding transformations. We combine the cost model with a genetic algorithm to compute the tile and pad factors that enhance the program performance. To validate our strategy, we ran experiments for a set of benchmarks on a large set of modern architectures. Our results show that this scheme is useful to optimize programs' performance. When compared to previous approaches, we observe that with a reasonable compile-time overhead, our approach gives significant performance improvements for all studied kernels on all architectures.
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