| 1. |
- Wheeler, D., et al.
(author)
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Deposition of HfO2 on InAs by atomic-layer deposition
- 2009
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In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 86:7-9, s. 1561-1563
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Conference paper (peer-reviewed)abstract
- Metal-oxide-semiconductor (MOS) capacitors are formed on bulk InAs substrates by atomic-layer deposition (ALD) of HfO2. Prior to film growth, InAs substrates receive a wet-chemical treatment of HCl, buffered HF (BHF), or (NH4)(2)S. Hafnium dioxide films are grown using 75 ALD cycles with substrate temperatures of 100, 200, and 300 degrees C. Substrate temperature is found to have a significant influence on the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the capacitors, while the influence of substrate pretreatment manifests itself in interface trap density, D-it, as measured by the Terman method. (C) 2009 Elsevier B.V. All rights reserved.
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| 2. |
- Caroff, Philippe, et al.
(author)
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InAs film grown on Si(111) by Metalorganic Vapor Phase Epitaxy
- 2008
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In: Journal of Physics: Conference Series. - : IOP Publishing. - 1742-6588 .- 1742-6596. ; 100, s. 042017-042017
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Conference paper (peer-reviewed)abstract
- We report the successful growth of high quality InAs films directly on Si( 111) by Metal Organic Vapor Phase Epitaxy. A nearly mirror-like and uniform InAs film is obtained at 580 C for a thickness of 2 mu m. We measured a high value of the electron mobility of 5100 cm(2)/Vs at room temperature. The growth is performed using a standard two-step procedure. The influence of the nucleation layer, group V flow rate, and layer thickness on the electrical and morphological properties of the InAs film have been investigated. We present results of our studies by Atomic Force Microscopy, Scanning Electron Microscopy, electrical Hall/van der Pauw and structural X-Ray Diffraction characterization.
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| 3. |
- Wernersson, Lars-Erik, et al.
(author)
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A combined chemical vapor deposition and rapid thermal diffusion process for SiGe Esaki diodes by ultra-shallow junction formation
- 2005
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In: IEEE Transactions on Nanotechnology. - 1536-125X. ; 4:5, s. 594-598
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Journal article (peer-reviewed)abstract
- SiGe Esaki diodes have been realized by rapid thermal diffusion of phosphorous into an SiGe layer grown by ultra-high-vacuum chemical-vapor-deposition on an Si p(+)-substrate for the first time. The phosphorous-doped SiGe forms the n(+)-electrode, while heavily boron-doped Si0.74Ge0.26 and Si substrate is used for the p(+) electrode. The diodes show a peak current density of 0.18 kA/cm(2), a current peak-to-valley ratio of 2.6 at room temperature, and they exhibit only a weak temperature dependence. Cross-sectional transmission microscopy showed a good crystalline quality of the strained Si0.74Ge0.26 layer even after the diffusion step at 900 degrees C.
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| 4. |
- Wernersson, Lars-Erik, et al.
(author)
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SiGe Esaki tunnel diodes fabricated by UHV-CVD growth and proximity rapid thermal diffusion
- 2004
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In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 1350-911X .- 0013-5194. ; 40:1, s. 83-85
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Journal article (peer-reviewed)abstract
- A process for realisation of SiGe Esaki diodes in layers grown by ultra-high vacuum chemical vapour deposition has been developed and the first Esaki diodes are reported for this growth method. Intrinsic SiGe-layers are grown on highly boron-doped p(+)-Si layers, while post-growth proximity rapid thermal diffusion of phosphorous into the SiGe is employed to form an n(+)-layer. Tunnel diodes with a depletion layer width of about 6 nm have been realised in Si0.74Ge0.26, showing a peak current density of 0.18 kA/cm(2) and a current peak-to-valley ratio of 2.6 at room temperature.
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| 5. |
- Zhang, J., et al.
(author)
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Projected performance of experimental InAs/GaAsSb/GaSb TFET as millimeter-wave detector
- 2018
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In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - 9781538637654 ; 2018-March, s. 1-2
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Conference paper (peer-reviewed)abstract
- Based on measurements of a vertical nanowire InAs/GaAsSb/GaSb tunneling field-effect transistor (TFET) that exhibited minimum subthreshold swing of 48 mV/dec and a record high I60 of 0.31 μA/μm, a SPICE model has been generated to allow an experimentally-based prediction of the nanowire TFET technology. At 30 GHz the detector has been simulated to reveal a sensitivity of 4.8 kV/W biased near zero volts (VGS =-0.06 V, VDS = 0.1 V). A maximum sensitivity of over 4000 kV/W has been obtained under biased conditions. These results exceed prior measurements of an In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction TFET by over an order of magnitude.
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