| 1. |
- Klefsjö, Bengt
(författare)
-
Testing against a change in the NBUE property
- 1989
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 29:4, s. 559-570
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Tidskriftsartikel (refereegranskat)abstract
- A life distribution F with survival function F=1-F, finite mean μ and mean residual life e(t) is said to be NBUE (NWUE) if e(t)⩽(⩾)μ for t⩾0. This NBUE (NWUE) property can equivalently be characterized by the fact that φ(u)⩽(⩾)u for 0⩽u⩽1, where φ(u) is the scaled TTT-transform of F. A generalization of the NBUE and NWUE properties is that there is a value of s such that φ(u)⩾u for 0⩽u⩽p and φ(u)⩽u for p⩽u⩽1, or vice versa. This means a trend change in the NBUE property. This generalized aging property is called the NBUE-NWUE property. In this paper the authors present and study a test statistic intended for testing exponentiality (i.e. φ(u)=u for 0⩽u⩽1) against this NBUE-NWUE property. The asymptotic normality of the test statistic, suitably normalized, is established and a simulation study is presented (20 refs.)
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| 2. |
- Lutz, J., et al.
(författare)
-
Dynamic avalanche and reliability of high voltage diodes
- 2003
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Ingår i: Microelectronics and reliability. - 0026-2714 .- 1872-941X. ; 43:4, s. 529-536
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Tidskriftsartikel (refereegranskat)abstract
- Diode failures are a limiting factor for the reliability of power circuits. One failure reason is dynamic avalanche, Dynamic avalanche can be distinguished in three degrees, and some designs are rugged up to the third degree. Design modifications for improving the dynamic ruggedness and suitable test conditions are proposed.
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| 3. |
- Sanden, M., et al.
(författare)
-
Decreased low frequency noise by hydrogen passivation of polysilicon emitter bipolar transistors
- 2000
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Ingår i: Microelectronics and reliability. - 0026-2714 .- 1872-941X. ; 40:11, s. 1863-1867
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Tidskriftsartikel (refereegranskat)abstract
- The effect of hydrogen passivation by forming gas annealing (FGA) on the bipolar junction transistor low frequency noise was investigated. The results demonstrated a reduced 1/f noise component by a factor of five after FGA, which resulted in a reduced corner frequency. An equivalent input noise spectral density (S-IB) dependence on base current (IB) of S-IB similar to I-B(2) and on emitter area (A(E)) of S-IB similar to A(E)(-1) was observed, both before and after FGA. The interpretations of the results were (a) the 1/f noise was due to carrier number fluctuation, (b) the noise sources were homogeneously distributed over the polysilicon/monosilicon emitter interfacial oxide, and
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| 4. |
- Sanden, M., et al.
(författare)
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Lateral base design rules for optimized low-frequency noise of differentially grown SiGe heterojunction bipolar transistors
- 2001
-
Ingår i: Microelectronics and reliability. - 0026-2714 .- 1872-941X. ; 41:6, s. 881-886
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Tidskriftsartikel (refereegranskat)abstract
- The low-frequency noise dependence on lateral design parameters was investigated for SiGe heterojunction bipolar transistors fabricated by differential epitaxy. The low-frequency noise was found to vary substantially as a function of the extrinsic base design. The dominant noise sources were located either at the interface between the polycrystalline and epitaxial Si/SiGe base, in the epitaxial Si/SiGe base link region, in the base-emitter depletion region, or at the thin SiO2 interface layer between the polysilicon and monosilicon emitter. Boron was found to passivate interfacial traps, acting as low-frequency noise sources. Generation-recombination noise with a strong dependence on the lateral electrical field was observed for some of the designs.
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| 5. |
- Zheng, Li-Rong, et al.
(författare)
-
System-on-package : a broad perspective from system design to technology development
- 2003
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 43:8, s. 1339-1348
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we summarize and analyze main challenges towards system-on-package (SoP) integration with a broad perspective from system design to technology development. We see that the future SoP faces a main challenge of changed system architecture that will be different from today's personal computer or PC-based systems. It is likely that communication-network based system architectures will be interesting to future SoP platforms. Second, we find that a major paradigm shift will occur in design methodology for SoP integration that emphasizes a coherent co-design of chip, package and system in a mixed signal environment and in combination with new issues such as virtual components integration. On the technology side, the major challenges will be power dissipation and system cooling, low-cost and thermal-matched high-density interconnect substrates, as well as low-cost passive components integration. Finally, we present some research examples that aim to cope with these new challenges on a strategic basis.
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| 6. |
- Abermann, S., et al.
(författare)
-
Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics
- 2007
-
Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 536-539
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Tidskriftsartikel (refereegranskat)abstract
- In this work we compare the impacts of nickel (Ni), titanium-nitride (TiN), molybdenum (Mo), and aluminium (Al), gates on MOS capacitors incorporating HfO2- or ZrO2-dielectrics. The primary focus lies on interface trapping, oxide charging, and thermodynamical stability during different annealing steps of these gate stacks. Whereas Ni, Mo, and especially TIN are investigated as most promising candidates for future CMOS devices, Al acted as reference gate material to benchmark the parameters. Post-metallization annealing of both, TiN- and Mo-stacks, resulted in very promising electrical characteristics. However, gate stacks annealed at temperatures of 800 degrees C or 950 degrees C show thermodynamic instability and related undesirable high leakage currents.
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| 7. |
- Akbari, Saaed, et al.
(författare)
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Effect of PCB cracks on thermal cycling reliability of passive microelectronic components with single-grained solder joints
- 2019
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 93, s. 61-71
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Tidskriftsartikel (refereegranskat)abstract
- Lead-free tin-based solder joints often have a single-grained structure with random orientation and highly anisotropic properties. These alloys are typically stiffer than lead-based solders, hence transfer more stress to printed circuit boards (PCBs) during thermal cycling. This may lead to cracking of the PCB laminate close to the solder joints, which could increase the PCB flexibility, alleviate strain on the solder joints, and thereby enhance the solder fatigue life. If this happens during accelerated thermal cycling it may result in overestimating the lifetime of solder joints in field conditions. In this study, the grain structure of SAC305 solder joints connecting ceramic resistors to PCBs was studied using polarized light microscopy and was found to be mostly single-grained. After thermal cycling, cracks were observed in the PCB under the solder joints. These cracks were likely formed at the early stages of thermal cycling prior to damage initiation in the solder. A finite element model incorporating temperature-dependant anisotropic thermal and mechanical properties of single-grained solder joints is developed to study these observations in detail. The model is able to predict the location of damage initiation in the PCB and the solder joints of ceramic resistors with reasonable accuracy. It also shows that the PCB cracks of even very small lengths may significantly reduce accumulated creep strain and creep work in the solder joints. The proposed model is also able to evaluate the influence of solder anisotropy on damage evolution in the neighbouring (opposite) solder joints of a ceramic resistor.
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| 8. |
- Buiu, O., et al.
(författare)
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Extracting the relative dielectric constant for "high-k layers" from CV measurements : Errors and error propagation
- 2007
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 678-681
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Tidskriftsartikel (refereegranskat)abstract
- The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., kappa value) from capacitance-voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-rc dielectric and the silicon substrate is a factor that affects - in general - the assessment of the electrical data, as well as the extraction of rc. A methodology which accounts for this transition layer and the errors related to other parameters involved in the k value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO2/SiOx/Si structures produced in different conditions.
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| 9. |
- Conseil-Gudla, Helene, et al.
(författare)
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Transient risk of water layer formation on PCBAs in different climates: Climate data analysis and experimental study
- 2022
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Ingår i: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 136
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Tidskriftsartikel (refereegranskat)abstract
- The reliability of electronic devices depends on the environmental loads at which they are exposed. Climatic conditions vary greatly from one geographical location to another (from hot and humid to cold and dry areas), and the temperature and humidity vary from season to season and from day to day. High levels of temperature and relative humidity mean high water content in the air, but saturated conditions (i.e. 100 % RH) can also be reached at low temperatures. This paper analyses the relationship between temperature, dew point temperature, their difference (here called ΔT), and occurrence and time period of dew point closeness to temperature on transient condensation effects on electronics.This paper has two parts: (i) Data analysis of typical climate profiles within the different zones of the Köppen -Geiger classification to pick up conditions where ΔT is very low (for example ≤0.4 °C). Various summary statistics of these events are calculated in order to assess the temperature at which these events happen, their durations and their frequency and (ii) Empirical investigation of the effect of ΔT ≤ 0.4 °C on the reliability of electronics by mimicking an electronic device, for which the time period of the ΔT is varied in one set of experiments, and the ambient temperature is varied in the other. The effect of the packaging of the electronics is also studied in this section.The statistical study of the climate profiles shows that the transient events (ΔT ≤ 0.4 °C) occur in almost every location, at different temperature levels, with a duration of at least one observation (where observations were hourly in the database). The experimental results show that presence of the enclosure, cleanliness and bigger pitch size reduce the levels of leakage current, while similar high levels of leakage current are observed for the different durations of the transient events, indicating that these climatic transient conditions can have a big impact on the electronics reliability.
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| 10. |
- Edwards, Michael, 1986, et al.
(författare)
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The shear strength of nano-Ag sintered joints and the use of Ag interconnects in the design and manufacture of SiGe-based thermo-electric modules
- 2015
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 55:5, s. 722-732
-
Tidskriftsartikel (refereegranskat)abstract
- Thermo-electric modules (TEMs) can be used to convert heat into electricity by utilizing the Seeback effect. It is now possible to buy BiTe thermo-electric modules that can operate up to temperatures of around 300 °C. However, many applications, such as the harvesting of excess gas turbine heat, may occur at higher temperatures. Therefore, new materials and manufacturing processes need to be developed to produce packaged TEMs that can operate at a maximum operating temperature of 650 °C. Two critical areas in the manufacture of a SiGe TEM are the choice and strength of materials used to both sintered joint the TE material to the rest of the module and the metal used for the interconnects. The interconnection material needs to be sufficiently strong to withstand large temperature fluctuations while maintaining a low contact resistance, as well as being compatible with the nano-Ag sintered joint. Shear force tests of the sintered thermo electrical leg material showed that the joints are brittle when sintered to W metallized AlN substrates are used and ductile fracture behavior when sintered to Cu metallized AlN substrates using the NanoTach K nano silver paste. Almost all of the joints were found to be brittle when using the NachTach X nano silver paste. Shear testing of the sintered joints showed that the X paste joints were variable in strength and stiffness, having a typical Young's modulus between 10 and 100 MPa at room temperature. The K paste joints were stiffer, but had a similar strength as compared to the X paste joints.
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| 11. |
- Hosseini, S. M., et al.
(författare)
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Residual stress measurement through the thickness of ball grid array microelectronics packages using incremental hole drilling
- 2019
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Ingår i: Microelectronics and reliability. - : Elsevier Ltd. - 0026-2714 .- 1872-941X. ; 102
-
Tidskriftsartikel (refereegranskat)abstract
- Microelectronic packages typically consist of several layers of polymer, silicon, and composite materials, which are bonded together under heat and pressure. The mismatch in thermo-mechanical properties between different layers can induce significant residual stresses in the fabrication process that may lead to delamination at the interface between the bonded layers. Therefore, it is important to develop a reliable method to determine residual stresses. In this study, incremental hole drilling method was used to determine fabrication-induced residual stresses in a ball grid array (BGA) microelectronics package. First, a small hole was drilled in several steps at the center of a strain gauge rosette bonded to the surface of the BGA package. This released residual stresses trapped at each depth increment and deformed the component. The corresponding surface strains were measured in three directions using rosette gauges. Then, the residual stress was calculated based on the integral method, in which the measured strains are converted to the residual stresses using a calibration matrix whose elements are obtained from a finite element model. The three in-plane components of the residual stress through the thickness of different layers of a BGA package, including molding compound, silicon chip, die attach, and the composite substrate, were reported based on the incremental hole drilling method. These findings show that the incremental hole drilling method can be used as a reliable method to estimate the residual stresses over the entire thickness of microelectronic packages, and evaluate their effect on the reliability under service conditions.
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| 12. |
- Johansson, Jonas, et al.
(författare)
-
Investigation on thermal fatigue of SnAgCu, Sn100C, and SnPbAg solder joints in varying temperature environments
- 2014
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 54:11, s. 2523-2535
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Tidskriftsartikel (refereegranskat)abstract
- Thermal cycling tests have been performed for a range of electronic components intended for avionic applications, assembled with SAC305, SN100C and SnPbAg solder alloys. Two temperature profiles have been used, the first ranging between −20 °C and +80 °C (TC1), and the second between −55 °C and +125 °C (TC2). High level of detail is provided for the solder alloy composition and the component package dimensions, and statistical analysis, partially supported by FE modeling, is reported. The test results confirm the feasibility of SAC305 as a replacement for SnPbAg under relatively benign thermomechanical loads. Furthermore, the test results serve as a starting point for estimation of damage accumulation in a critical solder joint in field conditions, with increased accuracy by avoiding data reduction. A computationally efficient method that was earlier introduced by the authors and tested on relatively mild temperature environments has been significantly improved to become applicable on extended temperature range, and it has been applied to a PBGA256 component with SAC305 solder in TC1 conditions. The method, which utilizes interpolated response surfaces generated by finite element modeling, extends the range of techniques that can be employed in the design phase to predict thermal fatigue of solder joints under field temperature conditions.
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| 13. |
- Khan, Sajid, et al.
(författare)
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A symmetric D flip-flop based PUF with improved uniqueness
- 2020
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Ingår i: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 106
-
Tidskriftsartikel (refereegranskat)abstract
- Physically unclonable functions (PUF) emerged as security primitives that generate high entropy, temper resilient bits for security applications. However, the implementation area budget limits their use in lightweight applications such as IoT, RFID, and biomedical applications. In the form of SRAM or D flip-flop, intrinsic PUFs are abundantly available in almost all of the designs. Being an integral part of the design, they can be used with compromised performance. In this work, to address the usage of intrinsic PUF, a D flip-flop based lightweight PUF is proposed. The proposed architecture is implemented on 40 nm CMOS technology. The simulation results show that it offers a uniqueness of 0.502 and the worst-case reliability of 95.89% at high temperature 125 °C and 97.89% at a supply voltage of 1.2 V. To evaluate the performance of various PUF architectures, A novel term, the uniqueness-to-reliability ratio, is proposed. When compared to the conventional D flip-flop, it offers 4.491 times more uniqueness and 127.74 times more uniqueness-to-reliability ratio with the same layout area. Since it uses the symmetrical structure, unlike other architectures, the proposed architecture does not require any post-processing schemes for bias removal, which further saves the silicon area. To verify the functional correctness of the simulation results, an FPGA implementation of the conventional and proposed D Flip-flop is also presented.
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| 14. |
- Khan, Sajid, et al.
(författare)
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D flip-flop based TRNG with zero hardware cost for IoT security applications
- 2021
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Ingår i: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 120
-
Tidskriftsartikel (refereegranskat)abstract
- System-on-chips (SoCs) for the Internet of things (IoT) applications require hardware-based integrated random number generators for the secure transmission of information. However, they have limited hardware and power budget, which limits the use of on-chip dedicated True Random Number Generator (TRNG). In this work, a symmetric D flip-flop with integrated TRNG is proposed. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers good randomness with low energy-per-bit. In addition, the circuit has passed all the tests of NIST without any post-processing. When compared with the conventional D flip-flop, it has almost negligible area overhead that is only 0.14%. An FPGA implementation is also presented as a proof of concept that confirms the simulation results. Advanced Encryption Standard (AES) key expansion algorithm is also implemented to demonstrate the dual usage of the proposed D flip-flop.
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| 15. |
- Lemme, Max C., 1970-, et al.
(författare)
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Comparison of metal gate electrodes on MOCVD HfO2
- 2005
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 45:5-6, s. 953-956
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Tidskriftsartikel (refereegranskat)abstract
- Metal gate electrodes of sputtered aluminum (At), titanium nitride (TiN) and nickel aluminum nitride (NiAlN) are investigated in this work. They are compared with respect to their compatibility with metal organic chemical vapor deposited (MOCVD) hafnium dioxide (HfO2) gate dielectrics. TiN, with a midgap work function of 4.65 eV on SiO2, exhibits promising characteristics as metal gate on HfO2. In addition, encouraging results are presented for the ternary metal NiAlN, whereas classic At electrodes are found unstable in conjunction with HfO2.
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| 16. |
- Lindgren, Mats, et al.
(författare)
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Application of simulation-based decision making in product development of an RF module
- 2007
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:2-3, s. 302-309
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents results of simulation-based design evaluation for thermal and thermo-mechanical performance and cost of packaging technology of a RF module for automotive application. Combination of thermal, thermo-mechanical and cost analysis within the multi-attribute decision making enabled design ranking and revealed two MCM-L/D and MCM-D designs with wire bonding assembly preferred for use in automotive applications for different temperature environments. Simulation-based design guidelines were developed for designing electronic modules exhibiting good thermal and thermo-mechanical performance. By application-based partitioning of the importance weights assigned to the reliability and cost criteria, the guidelines were extended to cover other application areas.
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| 17. |
- Muhammad, N., et al.
(författare)
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Remaining useful life (RUL) estimation of electronic solder joints in rugged environment under random vibration
- 2020
-
Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 107
-
Tidskriftsartikel (refereegranskat)abstract
- The remaining useful life (RUL) of electronic modules under the influence of rugged random-vibration and operational conditions is investigated in this paper. The effects of storage conditions and soft failures, caused by the vibrations to solder joints of a printed circuit board (PCB) are analyzed. The RUL is estimated with the help of vibration testing and finite element analysis techniques. Keeping in view the standard and working environmental conditions, the PCB of a power distribution module is subjected to random and sine vibrations. Besides the significance of fatigue damage and RUL estimation of solder joints, caused by storage or operation for a period of five years has not been addressed in existing literature so far. The current study performs the modal analysis to find the natural frequencies, mode shapes, and participation factor ratios of a PCB and its components. These natural frequencies are subsequently verified via comparison with experimental sine sweep results. A random vibration test over the frequency range from 10 Hz to 2000 Hz is also applied for recording the time-to-failure ratio of the PCB. Moreover, the spectrum analysis is performed using the commercial ANSYS software, to assess the acceleration response and the stress power spectral density (PSD) of the critical solder joints. The stress PSD is then used to estimate the random vibration fatigue damage of the solder joint. The calculated fatigue life, based on the modified Miner's rule and the Basquin power-law conform to the actual random vibration testing results.
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| 18. |
- Rocchetta, Roberto, et al.
(författare)
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A survey on LED Prognostics and Health Management and uncertainty reduction
- 2024
-
Ingår i: Microelectronics and reliability. - : Elsevier Ltd. - 0026-2714 .- 1872-941X. ; 157
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Forskningsöversikt (refereegranskat)abstract
- Hybrid Prognostics and Health Management (PHM) frameworks for light-emitting diodes (LEDs) seek accurate remaining useful life (RUL) predictions by merging information from physics-of-failure laws with data-driven models and tools for online monitoring and data collection. Uncertainty quantification (UQ) and uncertainty reduction are essential to achieve accurate predictions and assess the effect of heterogeneous operational-environmental conditions, lack of data, and noises on LED durability. Aleatory uncertainty is considered in hybrid frameworks, and probabilistic models and predictions are applied to account for inherent variability and randomness in the LED lifetime. On the other hand, hybrid frameworks often neglect epistemic uncertainty, lacking formal characterization and reduction methods. In this survey, we propose an overview of accelerated data collection methods and modeling options for LEDs. In contrast to other works, this review focuses on uncertainty quantification and the fusion of hybrid PHM models with optimal design of experiment methods for epistemic uncertainty reduction. In particular, optimizing the data collection with a combination of statistical optimality criteria and accelerated degradation test schemes can substantially reduce the epistemic uncertainty and enhance the performance of hybrid prognostic models.
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| 19. |
- Tegehall, Per-Erik, et al.
(författare)
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Impact of laminate cracks under solder pads on the fatigue lives of ball grid array solder joints
- 2015
-
Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 55:11, s. 2354-2370
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Tidskriftsartikel (refereegranskat)abstract
- This paper reports how the solder joint fatigue lives of three types of lead free plastic BGA components were affected by cracks formed in the printed PCB laminate during a thermal cycling test. The investigation showed that cracks were formed in the laminate for all three tested components. For one of the components having a large chip with solder joints located under the chip, very large cracks were formed in the PCB laminate beneath some solder pads.For lead-free solder joints to BGA components consisting of near eutectic solders based on tin, silver and copper, a large fraction of the solder joints may consist of one single tin grain. Due to anisotropy of tin grains, each solder joint to a BGA component will experience a unique stress condition which will make laminate cracking more likely under certain solder joints.The laminate cracks increased the flexibility of the joints and thereby improved the fatigue lives of the solder joints. Therefore, an estimation of the fatigue lives of solder joints to BGA components based on the results from a thermal cycling test may lead to an overestimation of the fatigue lives if products will be exposed to smaller temperature changes in the field than in the test.If cracks are not formed in the PCB laminate, or if the extent of cracking is small, single-grained solder joints can be expected to result in a high spread in failure distribution with some quite early failures.
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| 20. |
- Wolborski, Maciej, et al.
(författare)
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Characterisation of the Al2O3 films deposited by ultrasonic spray pyrolysis and atomic layer deposition methods for passivation of 4H–SiC devices
- 2006
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 46, s. 743-755
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Tidskriftsartikel (refereegranskat)abstract
- Al2O3 films were deposited using atomic layer deposition (ALD) and ultrasonic spray pyrolysis (USP) methods on p- and n-type Si substrates, n-type 4H–SiC substrates and 4H–SiC diodes for passivation studies. UV exposure in N2 atmosphere and 5% HF treatment were used as two separate surface preparation procedures prior to Al2O3 deposition. The films deposited with USP technique contain a large amount of fixed negative charge and are vulnerable to water incorporation into the material. The Al2O3 film prepared by ALD method shows much better uniformity and less negative charge. Decrease of the leakage current in the 4H–SiC diodes is observed after Al2O3 passivation using both methods.
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| 21. |
- You, S., et al.
(författare)
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Vertical GaN devices : Process and reliability
- 2021
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Ingår i: Microelectronics and reliability. - : Elsevier Ltd. - 0026-2714 .- 1872-941X. ; 126
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Tidskriftsartikel (refereegranskat)abstract
- This paper reviews recent progress and key challenges in process and reliability for high-performance vertical GaN transistors and diodes, focusing on the 200 mm CMOS-compatible technology. We particularly demonstrated the potential of using 200 mm diameter CTE matched substrates for vertical power transistors, and gate module optimizations for device robustness. An alternative technology path based on coalescence epitaxy of GaN-on-Silicon is also introduced, which could enable thick drift layers of very low dislocation density. © 2021
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| 22. |
- Chandran, Kumar
(författare)
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STANDBY REDUNDANCY AT SYSTEM AND COMPONENT LEVELS--A COMPARISON
- 1995
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 35:4, s. 751-752
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Tidskriftsartikel (refereegranskat)abstract
- This note compares the lifetime of a series and a parallel system when standby redundancy is provided at system and component level. The system lifetime is longer when standby redundancy is added at the component level for a series system whereas in the parallel system, standby redundancy at the system level is more efficient.
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| 23. |
- Andersson, Cristina, 1969, et al.
(författare)
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Effect of different temperature cycling profiles on the crack initiation and propagation and of Sn-3.5Ag wave soldered joints
- 2007
-
Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 47:2-3, s. 266-272
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Tidskriftsartikel (refereegranskat)abstract
- Temperature cycling of a test board with different electronic components was carried out at two different temperature profiles in a single-chamber climate cabinet. The first temperature profile ranged between 55 and 100 C and the second between 0 and 100 C. Hole mounted components and secondary side SMD components were wave soldered with an Sn–3.5Ag alloy. Joints of both dual in line(DIL) packages and ceramic chip capacitors were investigated. Crack initiation and propagation was analysed after every 500 cycles.In total, 6500 cycles were run at both temperature profiles and the observations from each profile were compared.For both kinds of components analysed, cracks were first visible for the temperature profile ranging between 55 and 100 C. For this temperature profile, and for DIL packages, cracks were visible already after 500 cycles, whereas for the other temperature profile, cracks initiated between 1000 and 1500 cycles. The cracks observed after 1500 cycles were visibly smaller for the temperature profile ranging between 0 and 100 C, concluding that crack initiation and propagation was slightly slower for this temperature profile. For the chip capacitors, cracks were first visible after 2000 cycles.
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| 24. |
- Dammann, M., et al.
(författare)
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Reliability and degradation mechanism of AlGaN/GaN HEMTs for next generation mobile communication systems
- 2009
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 49:5, s. 474-477
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Tidskriftsartikel (refereegranskat)abstract
- Excellent reliability performance of AlGaN/GaN HEMTs on SiC substrates for next generation mobile communication systems has been demonstrated using DC and RF stress tests on 8 x 60 mu m wide and 0.5 mu m long AlGaN/GaN HEMTs at a drain voltage of V-d = 50 V. Drain current recovery measurements after stress indicate that the degradation is partly caused by slow traps generated in the SiN passivation or in the HEMT epitaxial layers. The traps in the SiN passivation layer were characterized using high and low frequency capacitance-voltage (CV) measurements of MIS test structures on thick lightly doped GaN layers. (C) 2009 Elsevier Ltd. All rights reserved.
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| 25. |
- Kaczmarczyk, M., et al.
(författare)
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The influence of inhomogeneous trap distribution on results of DLTS study
- 2011
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 51:7, s. 1159-1161
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Tidskriftsartikel (refereegranskat)abstract
- A model is developed to describe how a narrow distribution of deep traps adjacent to quantum dots (QDs) influences the trap-related signals measured by frequency scanned deep level transient spectroscopy (FS-DLTS). By comparison with experiment, it is demonstrated that traps with a steep concentration gradient, positioned in the so called transition layer close to the edge of the depletion region ("lambda-effect"), have a strong influence on DLTS signal amplitudes. This is manifested by an extreme sensitivity to the change in the Fermi-level position when temperature is varied.
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| 26. |
- Kish, LB, et al.
(författare)
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Noise in nanotechnology
- 2000
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Ingår i: MICROELECTRONICS RELIABILITY. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0026-2714. ; 40:11, s. 1833-1837
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Tidskriftsartikel (refereegranskat)abstract
- The length scales dominating physical phenomena in nanotechnology are at the boundary of the macroscopic and microscopic world. Nanoobject formation is governed by a competition between deterministic and random forces. Therefore, classical physical noise
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| 27. |
- Nikolov, Dimitar, et al.
(författare)
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Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems
- 2014
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 54:5, s. 1022-1049
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Tidskriftsartikel (refereegranskat)abstract
- Increasing soft error rates for semiconductor devices manufactured in later technologies enforce the usage of fault tolerant techniques such as Roll-back Recovery with Checkpointing (RRC). As RRC introduces time overhead that increases the completion (execution) time, time constraints (deadlines) might be violated. This is a drawback for a class of computer systems where the correct operation is defined not only by providing the correct outcome of an operation but also by ensuring that the deadlines are met. These computer systems are referred to as real-time systems (RTSs). In general RTSs are classified as soft and hard RTSs depending on the consequences of violating the deadlines. For soft RTSs, where consequences of violating the deadlines are not very severe, research have focused on optimizing RRC and shown that it is possible to find the optimal number of checkpoints such that the average execution time (AET) is minimal. While minimal AET is important for soft RTSs, it is more important to provide a high probability that deadlines are met for hard RTSs, where consequences of violating the deadlines may be catastrophic. Hence, there is a need of probabilistic guarantees that jobs employing RRC complete before a given deadline. Traditionally, AET analysis have been used for soft RTSs and worst case execution time (WCET) analysis along with schedule feasibility have been used for hard RTSs. In this paper we introduce a reliability metric, Level of Confidence (LoC), which is equally applicable to both soft and hard RTS. LoC is used as a metric to evaluate to what extent a deadline is met. The main contributions of this paper are as follows. First, we present a mathematical framework for the evaluation of LoC when RRC is employed. Second, we provide a proof to verify the correctness of the proposed expression. Third, in the context of hard RTSs, we provide a method to obtain the optimal number of checkpoints that maximizes the LoC. Fourth, in the context of soft RTSs where the maximal LoC may not be needed, but instead some LoC requirement is needed, we present an optimization method for RRC that finds the number of checkpoints that results in the minimal completion time while the minimal completion time satisfies a given LoC requirement. Fifth, we use the proposed framework to evaluate and compare probabilistic guarantees when RRC is optimized towards soft RTSs.
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| 28. |
- Pooth, A., et al.
(författare)
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Morphological and electrical comparison of Ti and Ta based ohmic contacts for AlGaN/GaN-on-SiC HFETs
- 2017
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 68, s. 2-4
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Tidskriftsartikel (refereegranskat)abstract
- The morphology and impact on leakage currents of two different ohmic metal stacks for GaN based transistor devices is investigated in this work. The results have implications for the performance and reliability of a GaN transistor device. A low temperature Ta based and a higher temperature anneal Ti based metallization are compared. The low temperature process shows a smoother metal semiconductor interface together with several orders of magnitude lower vertical and lateral leakage compared to the conventional higher temperature process. In addition to the leakage tests, back bias ramping experiments are performed unveiling potential advantages of the conventional approach in mitigating current collapse. However the low leakage will enable higher voltage operation making the low temperature process the preferable choice for high power RF applications, if simultaneously current collapse can be controlled.
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| 29. |
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| 30. |
- Sun, Shuangxi, 1986, et al.
(författare)
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Mechanical and thermal characterization of a novel nanocomposite thermal interface material for electronic packaging
- 2016
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 56, s. 129-135
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a novel nanocomposite thermal interface material (Nano-TIM) consisting of a silver coated polyimide network and the indium matrix. One of the potential applications of this Nano-TIM is for heat dissipation in integrated circuits and electronic packaging. The shear strength of the Nano-TIM was investigated with DAGE-4000PSY shear tester. The shear strength of Nano-TIM is 4.5 MPa, which is 15% higher than that of the pure indium thermal interface material. The microstructure of cross-section and fracture surface was studied using Scanning Electron Microscopy (SEM). SEM pictures show a uniform polymer fiber distribution and solid interface between silver coated fibers and indium matrix. The thermal fatigue resistance of the Nano-TIM was evaluated by monitoring the variation of thermal interface resistance during the thermal cycling test (-40 to 125 degrees C). The thermal interface resistance was measured with a commercial xenon flash instrument after 100, 200, 300, 400, 500, and 1000 temperature cydes. The results-of thermal cycling test show that Nano-TIM presented consistent reliability performance with pure indium. Furthermore, the tooling effect of Nano-TIM was demonstrated through measuring the power chip temperature in the die attached structure by using an Infrared Camera. In the test, the Nano-TIM shows a comparable cooling effect to pure indium TIM for die attach applications in electronics packaging.
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| 31. |
- Wong, E. H., et al.
(författare)
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Interface and interconnection stresses in electronic assemblies – A critical review of analytical solutions
- 2017
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Ingår i: Microelectronics and Reliability. - : Elsevier BV. - 0026-2714. ; 79, s. 206-220
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Forskningsöversikt (refereegranskat)abstract
- The closed-form solutions for the interfacial stresses in assemblies constituting of two relatively stiff adherends sandwiching a relatively compliant adhesive layer are reviewed. The closed-form solutions are categorised into the “non-free edge solutions” that do not satisfy the nil-shear stress condition at the free edge of the adhesive and the “free edge solutions” that do. Being strength of material solutions, the non-free edge solutions are significantly simpler in form. On the other hand, the solutions tend to grossly underestimate the magnitude of the peeling stress at the free edge. Almost all classical “non-free edge solutions” suffer from two setbacks: (i) assumed ?a = 0, thus severely underestimating the magnitude of the peeling stress; and (ii) neglected the thickness of the adhesive in their formulation of the x-compliance of assemblies and the evaluation of the effective bending strain on adherends; the former leads to overestimation while the latter leads to gross underestimation of the shear stress (and hence, ?a(l)). These are demonstrated in a numerical exercise in which two widely followed “non-free edge solutions” and a simplified “free edge solutions” are benchmarked against the finite element analysis.
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