| 1. |
- Abedin, Ahmad, et al.
(författare)
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Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
- 2016
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Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-5862 .- 1938-6737. - 9781607685395 ; , s. 615-621
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Konferensbidrag (refereegranskat)abstract
- Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.
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| 2. |
- Abedin, Ahmad, et al.
(författare)
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Germanium on Insulator Fabrication for Monolithic 3-D Integration
- 2018
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Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 6:1, s. 588-593
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Tidskriftsartikel (refereegranskat)abstract
- A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
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| 3. |
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| 4. |
- Abedin, Ahmad, et al.
(författare)
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GOI fabrication for monolithic 3D integration
- 2018
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Ingår i: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538637654 ; , s. 1-3
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Konferensbidrag (refereegranskat)abstract
- A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.
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| 5. |
- Abedin, Ahmad, et al.
(författare)
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Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabrication
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- In this study, the application of epitaxially grown SixGe1-x films as etch stop layers in a germanium-on-insulator substrate fabrication flow is investigated. Layers with Ge contents from 15% to 70% were epitaxially grown on Si (1 0 0) using silane and germane. It was found that the Ge content in the films is independent of the growth temperature for fixed partial pressure ratios. At low growth temperatures the activation energy is found to be 1.8 eV which points to a hydrogen desorption limited growth rate mechanism. At growth temperatures of less than 500℃, the surface roughness is <1 nm. This surface roughness does not change when the films are grown on Ge substrates. Finally, a fully strained Si0.5Ge0.5 film was grown on Ge strain relaxed buffer at 450℃. This layer demonstrates etch selectivity of >400:1 towards Ge in diluted SC-1. This result enables the integration of the Si0.5Ge0.5 film as an etch stop layer for single crystalline germanium-on-insulator substrate fabrication.
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| 6. |
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| 7. |
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| 8. |
- Asadollahi, Ali, 1980-
(författare)
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Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
- 2018
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D. To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs. The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.
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| 9. |
- Asadollahi, Ali, et al.
(författare)
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Fabrication of relaxed germanium on insulator via room temperature wafer bonding
- 2014
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Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-6737. ; , s. 533-541
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Konferensbidrag (refereegranskat)abstract
- We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.
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| 10. |
- Asadollahi, Ali, et al.
(författare)
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Fabrication of strained Ge on insulator via room temperature wafer bonding
- 2014
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Ingår i: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014. - : IEEE Computer Society. - 9781479937189 ; , s. 81-84
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Konferensbidrag (refereegranskat)abstract
- This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
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| 11. |
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| 12. |
- Elahipanah, Hossein, et al.
(författare)
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A wafer-scale Ni-salicide contact technology on n-type 4H-SiC
- 2017
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Ingår i: ECS Journal of Solid State Science and Technology. - : Electrochemical Society. - 2162-8769 .- 2162-8777. ; 6:4, s. P197-P200
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.
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| 13. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
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A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
- 2017
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Ingår i: ECS Journal of Solid State Science and Technology. - : ECS. - 2162-8769 .- 2162-8777. ; 6:4, s. 197-200
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.
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| 14. |
- Garidis, Konstantinos, et al.
(författare)
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Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
- 2015
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Ingår i: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. - 9781479969111 ; , s. 165-168
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Konferensbidrag (refereegranskat)abstract
- We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.
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| 15. |
- Garidis, Konstantinos, et al.
(författare)
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Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation
- 2020
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Ingår i: Electronics. - : MDPI AG. - 2079-9292. ; 9:4
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial in situ doped Si0.73Ge0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si0.73Ge0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p+Si0.73Ge0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 1019 boron atoms/cm3. P+/n diodes were fabricated by selectively growing p+-Si0.73Ge0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p+/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p+/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p+/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10−2 A/cm2 which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p+/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.
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| 16. |
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| 17. |
- Jayakumar, Ganesh, et al.
(författare)
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Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing
- 2013
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Ingår i: ULIS 2013. - : IEEE. - 9781467348027 ; , s. 81-84
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Konferensbidrag (refereegranskat)abstract
- We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.
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| 18. |
- Jayakumar, Ganesh, et al.
(författare)
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Silicon nanowires integrated with CMOS circuits for biosensing application
- 2014
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 26-31
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Tidskriftsartikel (refereegranskat)abstract
- We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.
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