| 1. |
- Bleiker, Simon J., et al.
(författare)
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Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding
- 2016
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Ingår i: Micromachines. - Basel, Switzerland : Multidisciplinary Digital Publishing Institute (MDPI). - 2072-666X. ; 7:10, s. 192-
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Tidskriftsartikel (refereegranskat)abstract
- Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.
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| 2. |
- Lietaer, Nicolas, et al.
(författare)
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Wafer-level packaged MEMS switch with TSV
- 2011
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Konferensbidrag (refereegranskat)abstract
- A miniaturized wafer-level packaged MEMS acceleration switch with through silicon vias (TSVs) was fabricated, based on technologies suitable for harsh environment applications. The high aspect ratio TSVs were fabricated through the silicon-on-insulator (SOI) substrate prior to the fabrication of the MEMS structures. Doped polysilicon was used as the conductor for the TSVs, which has the advantage of a thermal coefficient of expansion that matches that of the silicon substrate material. The fragile MEMS structures were protected from the environment by wafer-level bonding of a glass cap using benzocyclobutene (BCB). The BCB layer which was spray-coated onto the patterned glass wafer provides a good bond strength and temperature stability. As opposed to having lateral interconnects at the interface between the cap wafer and the device wafer, the use of TSVs significantly reduces the footprint and allows flip-chip bonding of the devices onto a substrate. The bare MEMS chips were mounted directly onto a printed circuit board (PCB) thereby avoiding an entire packaging level and reducing the system complexity and cost. This was done using an isotropic conductive adhesive (ICA) based on metalized polymer spheres, which is believed to be an interconnect technology more suitable for harsh environments than metal-based BGA and CSP technology. The initial characterization of completed chips mounted on a PCB shows promising results.
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| 3. |
- Zimmer, Fabian, et al.
(författare)
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Fabrication of large-scale mono-crystalline silicon micro-mirror arrays using adhesive wafer transfer bonding
- 2009
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Ingår i: Proceedings of SPIE - The International Society for Optical Engineering. - : SPIE. ; , s. 720807-
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Konferensbidrag (refereegranskat)abstract
- Today,spatial light modulators (SLMs) based on individually addressable micro-mirrors playan important role for use in DUV lithography and adaptiveoptics. Especially the mirror planarity and stability are important issuesfor these applications. Mono-crystalline silicon as mirror material offers agreat possibility to combine the perfect surface with the goodmechanical properties of the crystalline material. Nevertheless, the challenge isthe integration of mono-crystalline silicon in a CMOS process withlow temperature budget (below 450°C) and restricted material options. Thus,standard processes like epitaxial growth or re-crystallization of poly-silicon cannotbe used. We will present a CMOS-compatible approach, using adhesivewafer transfer bonding with Benzocyclobutene (BCB) of a 300nm thinsilicon membrane, located on a SOI-donor wafer. After the bondprocess, the SOI-donor wafer is grinded and spin etched toremove the handle silicon and the buried oxide layer, whichresults in a transfer of the mono-crystalline silicon membrane tothe CMOS wafer. This technology is fully compatible for integrationin a CMOS process, in order to fabricate SLMs, consistingof one million individually addressable mono-crystalline silicon micro-mirrors. The mirrors,presented here, have a size of 16×16 µm2. Deflection isachieved by applying a voltage between the mirrors and theunderlying electrodes of the CMOS electronics. In this paper, wewill present the fabrication process as well as first investigationsof the mirror properties.
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| 4. |
- Zimmer, Fabian, et al.
(författare)
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One-Megapixel Monocrystalline-Silicon Micromirror Array on CMOS Driving Electronics Manufactured With Very Large-Scale Heterogeneous Integration
- 2011
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Ingår i: Journal of microelectromechanical systems. - 1057-7157 .- 1941-0158. ; 20:3, s. 564-572
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we demonstrate the first high-resolution spatial-light-modulator chip with 1 million tilting micromirrors made of monocrystalline silicon on analog high-voltage complementary metal-oxide-semiconductor driving electronics. This device, as result of a feasibility study, shows good optical and excellent mechanical properties. The micromirrors exhibit excellent surface properties, with a surface roughness below 1-nm root mean square. Actuated micromirrors show no imprinting behavior and operate drift free. Very large-scale heterogeneous integration was used to fabricate the micromirror arrays. The detailed fabrication process is presented in this paper, together with a characterization of the SLM devices. Large arrays of individually controllable micromirrors are the enabling component in high-perfomance mask-writing systems and promising for high throughput deep-ultraviolet maskless lithography systems. The adoption of new materials with enhanced characteristics is critical in meeting the challenging demands with regard to surface quality and operation stability in the future. Very large-scale heterogeneous integration may enable virtually any solid-state material to be integrated together with CMOS electronics. [2010-0272]
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| 5. |
- Zimmer, Fabian, et al.
(författare)
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Very large scale heterogeneous system integration for 1-megapixel mono-crystalline silicon micro-mirror array on CMOS driving electronics
- 2011
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Ingår i: 2011 IEEE 24th International Conference on Micro Electro Mechanical Systems (MEMS). - 9781424496327 ; , s. 736-739
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Konferensbidrag (refereegranskat)abstract
- In this paper we demonstrate the first high mirror-count 1-level spatial light modulator (SLM) chip with 1 million tilting micro-mirrors made of mono-crystalline silicon on analogue, high-voltage CMOS driving electronics. The device from a feasibility study shows good optical and excellent mechanical properties. The micro-mirrors exhibit excellent surface properties with a surface roughness below 1 nm RMS, actuated micro-mirrors show no imprinting behavior and operate drift-free. Very large scale heterogeneous system integration was used to fabricate the micro-mirror array; the process is presented in this paper together with a characterization of the fabricated device.
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