SwePub - sökning: WFRF:(Dentoni Litta Eugenio)

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1.	Dentoni Litta, Eugenio, et al. (författare) Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs 2013 Ingår i: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS). - : IEEE. - 9781467348027 ; , s. 122-125 Konferensbidrag (refereegranskat)abstract The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.
2.	Dentoni Litta, Eugenio, et al. (författare) Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks 2014 Ingår i: ULIS 2014. - 9781479937189 ; , s. 69-72 Konferensbidrag (refereegranskat)abstract Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.
3.	Dentoni Litta, Eugenio, et al. (författare) Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology 2014 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 20-25 Tidskriftsartikel (refereegranskat)abstract This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.
4.	Dentoni Litta, Eugenio, et al. (författare) Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs 2015 Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE conference proceedings. - 2168-6734. ; 3:5, s. 397-404 Tidskriftsartikel (refereegranskat)abstract Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO2/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiOx/HfO2 dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.
5.	Dentoni Litta, Eugenio, 1986-, et al. (författare) Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETs Annan publikation (övrigt vetenskapligt/konstnärligt)
6.	Dentoni Litta, Eugenio, et al. (författare) High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O 2013 Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 160:11, s. D538-D542 Tidskriftsartikel (refereegranskat)abstract A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.
7.	Dentoni Litta, Eugenio, et al. (författare) In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks 2012 Ingår i: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012. - : IEEE. - 9781467301916 ; , s. 105-108 Konferensbidrag (refereegranskat)abstract This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.
8.	Dentoni Litta, Eugenio, 1986- (författare) Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology 2014 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes.In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si.Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated.The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.
9.	Dentoni Litta, Eugenio, et al. (författare) (Invited) TmSiO As a CMOS-Compatible High-k Dielectric 2016 Ingår i: SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6. - : Electrochemical Society. - 9781607687146 ; , s. 79-89 Konferensbidrag (refereegranskat)abstract Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.
10.	Dentoni Litta, Eugenio, 1986-, et al. (författare) Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs 2013 Ingår i: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC). - : IEEE Computer Society. - 9781479906499 ; , s. 155-158 Konferensbidrag (refereegranskat)abstract Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.
11.	Dentoni Litta, Eugenio, et al. (författare) Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs 2015 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 24-29 Tidskriftsartikel (refereegranskat)abstract High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.
12.	Dentoni Litta, Eugenio, et al. (författare) Thulium silicate interfacial layer for scalable high-k/metal gate stacks 2013 Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 60:10, s. 3271-3276 Tidskriftsartikel (refereegranskat)abstract Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.
13.	Garidis, Konstantinos, et al. (författare) Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration 2015 Ingår i: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. - 9781479969111 ; , s. 165-168 Konferensbidrag (refereegranskat)abstract We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.
14.	Hellström, Per-Erik, et al. (författare) Interfacial layer engineering using thulium silicate/germanate for high-k/metal gate MOSFETs 2014 Ingår i: ECS Transactions. - : Electrochemical Society. ; , s. 249-260 Konferensbidrag (refereegranskat)abstract Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ∼20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.
15.	Litta, Eugenio Dentoni, et al. (författare) Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology 2015 Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 62:3, s. 934-939 Tidskriftsartikel (refereegranskat)abstract Integration of a high-k interfacial layer (IL) is a promising technological solution to improve the scalability of high-k/metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiOx/HfO2 nFETs (0.7 A/cm(2) at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and -0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiOx/HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm(2)/Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected life-times for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.
16.	Mitrovic, I. Z., et al. (författare) Atomic-layer deposited thulium oxide as a passivation layer on germanium 2015 Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 117:21 Tidskriftsartikel (refereegranskat)abstract A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge.
17.	Mitrovic, I. Z., et al. (författare) Interface engineering of Ge using thulium oxide : Band line-up study 2013 Ingår i: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 109, s. 204-207 Tidskriftsartikel (refereegranskat)abstract This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95 +/- 0.08 eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3 +/- 0.1 eV. A distinct absorption feature is observed at similar to 3.2 eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5 nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95 eV) and electrons (greater than 1.7 eV) for Ge MOSFET engineering.
18.	Olyaei, Maryam, et al. (författare) A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer 2013 Ingår i: 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013. - New York : IEEE conference proceedings. - 9781479906680 ; , s. 1-4 Konferensbidrag (refereegranskat)abstract Low-frequency noise of HfO2/TiN nMOSFETs with different SiO x interfacial layer (IL) thicknesses is presented. It is observed that chemically formed thin ILs (0.4 nm, 0.45 nm and 0.5 nm) show a noise level close to a reference thermal IL(1 nm). This is shown to relate to the dominant contribution of the high-k HfO2 traps in comparison to the IL traps. The average extracted values for effective trap densities in these wafers are Nt= 7×1018, 1×1019, 2×10 19 and 4.8×1019 for thermal oxide, 0.5 nm, 0.45 nm and 0.4 nm chemical oxide wafers respectively.
19.	Olyaei, Maryam, et al. (författare) Improved Low-frequency Noise for 0.3nm EOT Thulium Silicate Interfacial Layer 2014 Ingår i: Solid State Device Research Conference (ESSDERC), 2014 44th European. - : IEEE conference proceedings. - 9781479943760 ; , s. 361-364 Konferensbidrag (refereegranskat)abstract Low-frequency noise (LFN) of gate stacks with Tm2O3 high-k dielectric and thulium silicate (TmSiO) interfacial layer (IL) is investigated. The measured 1/f noise is compared to SiOx/HfO2 stacks with comparable IL thickness. Integration of a high-k thulium silicate IL provides a scaled EOT of 0.3nm with good mobility and interface quality, hence excellent LFN is obtained. The LFN noise for devices with TmSiO/Tm2O3 gate dielectric is reduced for nMOSFETs and comparable for pMOSFETs compared to SiOx/HfO2 devices.
20.	Olyaei, Maryam, et al. (författare) Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs 2015 Ingår i: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 36:12, s. 1355-1358 Tidskriftsartikel (refereegranskat)abstract Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3nm EOT interfacial layer (TmSiO) and two different bulk high-k dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate stack EOT was 1.2 nm and 0.65 nm for the Tm2O3 and HfO2 samples respectively. In general both gate stacks resulted in 1/f type of noise spectra and noise levels comparable to conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was 2.5×1017 cm-3eV-1 and 1.5×1017 cm-3eV-1 for TmSiO/HfO2 and TmSiO/Tm2O3 respectively. Therefore the best noise performance was observed for the gate stack with Tm2O3 bulk high-k layer and we suggest that the interface free single layer ALD fabrication scheme could explain this.
21.	Primetzhofer, Daniel, et al. (författare) Ultra-thin film and interface analysis of high-k dielectric materials employing Time-Of-Flight Medium Energy Ion Scattering (TOF-MEIS) 2014 Ingår i: Nuclear Instruments and Methods in Physics Research Section B. - : Elsevier BV. - 0168-583X .- 1872-9584. ; 332, s. 212-215 Tidskriftsartikel (refereegranskat)abstract We explore the potential of Time-Of-Flight Medium Energy Ion Scattering (TOF-MEIS) for thin film analysis and analyze possible difficulties in evaluation of experimental spectra. As a model system high-k material stacks made from ultra-thin films of HfO2 grown on a p-type Si (100) substrate with a 0.5 nm SiO2 interface layer have been investigated. By comparison of experimental spectra and computer simulations TOF-MEIS was employed to establish a depth profile of the films and thus obtaining information on stoichiometry and film quality. Nominal film thicknesses were in the range from 1.8 to 12.2 nm. A comparison of the results with those from other MEIS approaches is made. Issues regarding different combinations of composition and stopping power as well as the influence of channeling are discussed. As a supporting method Rutherford-Backscattering spectrometry (RBS) was employed to obtain the areal density of Hf atoms in the films.
22.	Vaziri, Sam, et al. (författare) Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors 2015 Ingår i: Nanoscale. - : Royal Society of Chemistry (RSC). - 2040-3364 .- 2040-3372. ; 7:30, s. 13096-13104 Tidskriftsartikel (refereegranskat)abstract Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.
23.	Vaziri, Sam, et al. (författare) Step tunneling-enhanced hot-electron injection in vertical graphene base transistors 2015 Ingår i: European Solid-State Device Research Conference. - : Editions Frontieres. - 9781467371339 ; , s. 198-201 Konferensbidrag (refereegranskat)abstract This paper presents promising current-voltage characteristics of semiconductor-insulator-graphene tunnel diodes as the hot-electron injection unit in graphene base transistors (GBTs). We propose that by using a bilayer tunnel barrier one can effectively suppress the defect mediated carrier transport while enhancing the hot-electron emission through Fowler-Nordheim tunneling (FNT) and step tunneling (ST). A stack of TmSiO/TiO2 (1 nm/ 5.5 nm) is sandwiched between a highly doped Si substrate and a single layer graphene (SLG) as the electrodes. This tunnel diode exhibits high current with large nonlinearity suitable for the application in GBTs.
24.	Zoller, C. J., et al. (författare) Characterization of high-k dielectrics using MeV elastic scattering of He ions 2015 Ingår i: Nuclear Instruments and Methods in Physics Research Section B. - : Elsevier BV. - 0168-583X .- 1872-9584. ; 347, s. 52-57 Tidskriftsartikel (refereegranskat)abstract We present a systematic comparison of two distinct ion-beam based methods for composition analysis of nanometer oxide films: ion-beam channeling and elastic scattering using nuclear resonances, both at MeV energies. Thin films of the technologically highly relevant high-k dielectrics HfO2 and HfAIO are characterized in the present study, with the additional aim of obtaining a better quantification of the Al content for the latter system. We show that both employed ion scattering methods enable a quantitative determination of the oxygen concentrations with typical uncertainties of about 5-10% in the oxygen fraction. The influence of various kinds of systematic inaccuracies in the evaluation procedure are discussed.
25.	Östling, Mikael, et al. (författare) Atomic layer deposition-based interface engineering for high-k/metal gate stacks 2012 Ingår i: ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. - : IEEE. - 9781467324724 ; , s. 6467643- Konferensbidrag (refereegranskat)abstract This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.
26.	Östling, Mikael, et al. (författare) Recent advances in high-k dielectrics and inter layer engineering 2014 Ingår i: Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. - 9781479932962 Konferensbidrag (refereegranskat)abstract State-of-the-art CMOS technology relies on the integration of multi-layer high-k/metal gate stacks in order to achieve high capacitance density while fulfilling the requirements in terms of gate leakage current density, interface state density, channel mobility, threshold voltage and reliability. Conventional SiOx/HfO2 gate dielectric stacks are capable of meeting the performance targets of current technology nodes and have been shown to possess sufficient short-term scalability, but solutions providing enhanced long-term scalability are actively researched, mostly via integration of higher-k oxides or high-k interfacial layers. This paper provides an overview of recent research efforts in this area, focusing on integration of high-k interfacial layers. We then analyze the potential scalability improvement which can be obtained through integration of thulium silicate as interfacial layer and summarize the main results supporting its applicability to future technology nodes.

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