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Numrering	Referens	Omslagsbild	Hitta
1.	Andersson, Oskar, et al. (författare) Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS 2013 Ingår i: Proceedings of the ESSCIRC (ESSCIRC), 2013. - 1930-8833. - 9781479906437 ; , s. 192-200 Konferensbidrag (refereegranskat)abstract Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.

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