| 11. |
- Ebrahimi, Masoumeh, et al.
(författare)
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Rescuing healthy cores against disabled routers
- 2014
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Konferensbidrag (refereegranskat)abstract
- A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.
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| 12. |
- Ejaz, Ahsen, et al.
(författare)
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Costs and benefits of flexibility in spatial division Circuit Switched Networks-on-Chip
- 2013
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Ingår i: NoCArc '13 Proceedings of the Sixth International Workshop on Network on Chip Architectures. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450323703 ; , s. 41-46
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Konferensbidrag (refereegranskat)abstract
- Although most Network-on-Chip (NoC) designs are based on Packet Switching (PS), the importance of Circuit Switching (CS) should not be underestimated. Many MPSoC executing real-time applications require an underlying communication backbone that can relay messages from one node to another with guaranteed throughput. Compared to PS, CS can provide guaranteed throughput with lower area and power overheads. It is also highly suited for applications where nodes transfer long messages. Spatial Division Multiplexing (SDM) can allow more efficient use of available network resources by dividing them among multiple simultaneous transactions. The network developed by Vali [1] has three design variations based on the number of sub-channels, has a predictable connection setup time, and uses CS to provide guaranteed throughput once a connection is established. In this paper we use this network as a basis to study the effect of flexibility based on SDM, on the performance of a CS networks. A network evaluation platform has been developed to configure and evaluate networks with a maximum of 8 sub-networks, with each sub-network comprising of 1, 2 or 4 sub-channels. We show that under uniform traffic pattern with requests of uniform random bandwidth (BW) requirement, a less flexible network outperforms a network with higher flexibility due to a phenomenon we call 'stray requests'. We conclude this paper by showing that under high network traffic, performance of our flexible networks can be as much as 113% better than HAGAR [2] and Liu's [3] network. Co
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| 13. |
- Eslami Kiasari, Abbas, et al.
(författare)
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A Framework for Designing Congestion-Aware Deterministic Routing
- 2010
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Ingår i: NoCArc '10 Proceedings of the Third International Workshop on Network on Chip Architectures. - New York, NY, USA : ACM. - 9781450303972 ; , s. 45-50
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Konferensbidrag (refereegranskat)abstract
- In this paper, we present a system-level Congestion-Aware Routing (CAR) framework for designing minimal deterministic routing algorithms. CAR exploits the peculiarities of the application workload to spread the load evenly across the network. To this end, we first formulate an optimization problem of minimizing the level of congestion in the network and then use the simulated annealing heuristic to solve this problem. The proposed framework assures deadlock-free routing, even in the networks without virtual channels. Experiments with both synthetic and realistic workloads show the effectiveness of the CAR framework. Results show that maximum sustainable throughput of the network is improved by up to 205% for different applications and architectures.
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| 14. |
- Eslami Kiasari, Abbas, et al.
(författare)
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Analytical approaches for performance evaluation of networks-on-chip
- 2012
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Ingår i: CASES'12 - Proceedings of the 2012 ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Co-located with ESWEEK. - New York, NY, USA : ACM. - 9781450314244 ; , s. 211-212
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Konferensbidrag (refereegranskat)abstract
- This tutorial reviews four popular mathematical formalisms - dataflow analysis, schedulability analysis, network calculus, and queueing theory - and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
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| 15. |
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| 16. |
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| 17. |
- Feng, Chaochao, et al.
(författare)
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Evaluation of Deflection Routing on Various NoC Topologies
- 2011
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Ingår i: Proceedings of the IEEE International Conference on ASIC (ASICON).
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose two novel deflection routing algorithms for de Bruijn and Spidergon NoCs and evaluate the performance of the deflection routing on 5 NoC topologies with different synthetic traffic patterns. We also synthesize the routers in various NoC topologies with TSMC 65nm technology. The evaluation results illustrate that the performance of deflection routing is susceptible to the network topology and traffic pattern. The results can also guide the NoC architect to choose the suitable NoC topology for the specific application.
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| 18. |
- Feng, Chaochao, et al.
(författare)
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FoN : Fault-on-Neighbor aware Routing Algorithm for Networks-on-Chip
- 2010
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Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2010. - 9781424466832 ; , s. 441-446
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Konferensbidrag (refereegranskat)abstract
- Reliability has become a key issue of Networks-on-Chip (NoC) as the CMOS technology scales down to the nanoscale domain. This paper proposes a Fault-on-Neighbor (FoN) aware deflection routing algorithm for NoC which makes routing decision based on the link status of neighbor switches within 2 hops to avoid fault links and switches. Simulation results demonstrate that in the presence of faults, the saturated throughput of the FoN switch is 13% higher on average than a cost-based deflection switch for 88 mesh. The average hop counts can be up to 1.7 less than the cost-based switch. The FoN switch is also synthesized using 65nm TSMC technology and it can work at 500MHz with small area overhead.
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| 19. |
- Grange, Matt, et al.
(författare)
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Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early-Chip Planning
- 2011
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Ingår i: 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). - 9781457713989 - 9781457713996 ; , s. 310-317
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Konferensbidrag (refereegranskat)abstract
- Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
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| 20. |
- Grange, Matt, et al.
(författare)
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Modeling the Efficiency of Stacked Silicon Systems : Computational, Thermal and Electrical Performance
- 2011
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Konferensbidrag (refereegranskat)abstract
- Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.
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