| 1. |
- Börjeson, Erik, 1984, et al.
(författare)
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Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations
- 2020
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Ingår i: 2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings. - 9781943580712
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Konferensbidrag (refereegranskat)abstract
- Using FPGA-accelerated simulations, we study the cycle-slip rate of 16QAM blind phase search implementations. While block averaging suffers from degraded BER when compared to sliding-window averaging, it results in lower cycle-slip rates and power dissipation.
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| 2. |
- Börjeson, Erik, 1984
(författare)
-
Implementation of Carrier Phase Recovery Circuits for Optical Communication
- 2020
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Fiber-optic links form a vital part of our increasingly connected world, and as the number of Internet users and the network traffic increases, reducing the power dissipation of these links becomes more important. A considerable part of the total link power is dissipated in the digital signal processing (DSP) subsystems, which show a growing complexity as more advanced modulation formats are introduced. Since DSP designers can no longer take reduced power dissipation with each new CMOS process node for granted, the design of more efficient DSPalgorithms in conjunction with circuit implementation strategies focused on power efficiency is required. One part of the DSP for a coherent fiber-optic link is the carrier phase recovery (CPR) unit, which can account for a significant portion of the DSP power dissipation, especially for shorter links. A wide range of CPR algorithms is available, but reliable estimates of their power efficiency is missing, making accurate comparisons impossible. Furthermore, much of the current literature does not account for the limited precision arithmetic of the DSP. In this thesis, we develop circuit implementations based on a range of suggested CPR algorithms, focusing on power efficiency. These circuits allow us to contrast different CPR solutions based not only on power dissipation, but also on the quality of the phase estimation, including fixed-point arithmetic aspects. We also show how different parameter settings affect the power efficiency and the implementation penalty. Additionally, the thesis includes a description of our field-programmable gate-array fiber-emulation environment, which can be used to study rare phenomena in DSP implementations, or to reach very low bit-error rates. We use this environment to evaluate the cycle-slip probability of a CPR implementation.
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| 3. |
- Börjeson, Erik, 1984, et al.
(författare)
-
VLSI Implementations of Carrier Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
- 2020
-
Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 38:14, s. 3616-3623
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Tidskriftsartikel (refereegranskat)abstract
- We present circuit implementations of blind phase search (BPS) carrier phase recovery (CPR) for M-QAM coherent optical receivers and highlight some BPS algorithm modifications necessary to obtain efficient VLSI circuits. In addition, we show how three key design parameters (input word length, number of test phases, and type and size of averaging window) affect the resulting implementation. To study design tradeoffs, we develop BPS CPR circuit netlists for a 32-GBaud system, using a 22-nm CMOS process technology: Our implementations reach energy efficiencies of around 1 pJ/bit for 16QAM up to 3 pJ/bit for 256QAM, at an SNR penalty of approximately 0.25 dB at a BER of 10^(−2). Furthermore, we present a circuit implementation of pilot-symbol-aided CPR, reaching 0.38 pJ/bit and 0.34 pJ/bit for 16QAM and 256QAM, respectively, at a slightly higher SNR penalty. The two CPR methods are also evaluated in terms of silicon area and scaling to higher-order modulation formats.
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| 4. |
- Fougstedt, Christoffer, 1990, et al.
(författare)
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ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers
- 2020
-
Ingår i: 2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings. - : Optical Society of America. - 9781943580712
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Konferensbidrag (refereegranskat)abstract
- We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5W, suggesting implementation feasibility in power-constrained form factors.
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| 5. |
- Larsson-Edefors, Per, 1967, et al.
(författare)
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Power-Efficient ASIC Implementation of DSP Algorithms for Coherent Optical Communication
- 2020
-
Ingår i: 2020 IEEE Photonics Society Summer Topical Meeting Series, SUM 2020 - Proceedings. ; July 2020
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Konferensbidrag (refereegranskat)abstract
- Coherent optical communication critically relies on efficient digital signal processing (DSP). We outline the application-specific integrated circuit (ASIC) implementation flow for DSP algorithms and discuss approaches to reducing the digital ASIC power dissipation of high-throughput DSP implementations for coherent fiber-optic communication systems.
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