| 1. |
- McMahon, J J, et al.
(författare)
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CMP compatibility of partially cured benzocyclobutene (BCB) for a via-first 3D IC process
- 2005
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Ingår i: Chemical-Mechanical Planarization-Integration, Technology and Reliability. - WARRENDALE, PA : MATERIALS RESEARCH SOCIETY. - 1558998209 ; , s. 63-68
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Konferensbidrag (refereegranskat)abstract
- Wafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a via-first 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-to-Cu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding. In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190 degrees C to 250 degrees C, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test.
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| 2. |
- Niklaus, Frank, et al.
(författare)
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Effects of bonding process parameters on wafer-to-wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding
- 2005
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Ingår i: Materials, Technology and Reliability of Advanced Interconnects-2005. - WARRENDALE, PA : MATERIALS RESEARCH SOCIETY. - 1558998160 ; , s. 393-398
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Konferensbidrag (refereegranskat)abstract
- Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 trim diameter wafers. Our baseline wafer bonding process with soft-baked BCB (similar to 35% cross-linked) has been modified to use partially cured (similar to 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 mu m (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.
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| 3. |
- Gutmann, R.J., et al.
(författare)
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Wafer-Level Via-First 3D Integration with Hybrid-Bonding of Cu/BCB Redistribution Layers
- 2005
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Three-dimensional (3D) integration with through-die viasoffer improved electrical performance compared to edgeconnectedwire bonds in stacked-die assemblies for wirelessapplications. Monolithic wafer-level 3D integration offersthe potential for a high density of micron-sized through-dievias necessary for highest performance memory stacks,microprocessors with large L2 caches and ASICs with largeembedded memories. In addition, such wafer-leveltechnologies offer the potential of lowest cost in largemanufacturing volume of any heterogeneous integrationplatform, incorporating the inherent low cost of monolithicIC interconnectivity. After a brief summary of current wafer-level 3D integrationplatforms, a recently introduced platform that offers theprocess integration advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength andenvironmental robustness of dielectric adhesive bondingusing benzocyclobutene (BCB) is discussed. Criticalprocessing challenges of the new platform include BCBpartial curing compatible with damascene patterning, postdamascene-patterning cleaning and surface activation,bonding process parameters, and wafer-level planarizationrequirements. The inherent incorporation of a redistributionlayer into the bonding layer process further reduces theprocess flow and is compatible with wafer-level packaging(WLP) technologies.
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| 4. |
- Niklaus, Frank, et al.
(författare)
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Wafer-Level 3D Integration Technology Platforms for ICs and MEMS
- 2005
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Ingår i: TWENTY SECOND INTERNATIONAL VLSI MULTILEVEL INTERCONNECTION (VMIC). ; , s. 486-493
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Wafer-level three-dimensional (3D) integration is an emerging technology to increase theperformance and functionality of integrated circuits (ICs) and microelectromechanical systems(MEMS). In ICs, wafer-level 3D integration based on wafer bonding offers the potential for a highdensity of micron-sized through-die vias necessary for highest performance memory stacks,microprocessors with large L2 caches and ASICs with large embedded memories. In MEMS devices,wafer-level 3D integration based on wafer bonding offers the potential for integrating highperformance transducer materials such as various monocrystalline semiconductor materials withelectronic circuits for arrayed, highly integrated sensor and actuator components. This invited paperpresents an overview of current wafer-level 3D integration platforms that use wafer bonding withpolymer adhesives for ICs and MEMS applications.
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