| 1. |
- Li, Junjie, et al.
(författare)
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A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm
- 2020
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Ingår i: Materials. - : MDPI AG. - 1996-1944. ; 13:3
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Tidskriftsartikel (refereegranskat)abstract
- Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.
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| 2. |
- Radamson, Henry H., et al.
(författare)
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State of the Art and Future Perspectives in Advanced CMOS Technology
- 2020
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Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 10:8
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Forskningsöversikt (refereegranskat)abstract
- The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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| 3. |
- Wang, Guilei, et al.
(författare)
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Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)
- 2020
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 26-33
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.
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