| 1. |
- Candaele, Bernard, et al.
(författare)
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Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
- 2010
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Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
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Konferensbidrag (refereegranskat)abstract
- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
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| 2. |
- Candaele, Bernard, et al.
(författare)
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The MOSART Mapping Optimization for multi-core Architectures
- 2011
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Ingår i: VLSI 2010 Annual Symposium. - Dordrecht : Springer Publishing Company. ; , s. 181-195
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Konferensbidrag (refereegranskat)abstract
- MOSART project addresses two main challenges of prevailing architectures: (i) Theglobal interconnect and memory bottleneck due to a single, globally shared memorywith high access times and power consumption; (ii) The difficulties in programmingheterogeneous, multi-core platforms MOSART aims to overcome these through amulti-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled,optimized and customized together to achieve diverse energy, performance, cost andsize requirements of different classes of applications. MOSART achieves this by:(i) Providing platform support for management of abstract data structures includingmiddleware services and a run-time data manager for NoC based communicationinfrastructure; (ii) Developing tool support for parallelizing and mapping applicationson the multi-core target platform and customizing the processing cores for theapplication.
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| 3. |
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| 4. |
- Ellervee, Peeter, et al.
(författare)
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Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
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Ingår i: Proc. of IEEE ASIC-conference, 1994.
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Konferensbidrag (refereegranskat)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
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| 5. |
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| 6. |
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| 7. |
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| 8. |
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| 9. |
- Hellberg, Lars, et al.
(författare)
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System oriented VLSI curriculum at KTH
- 1997
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Ingår i: ; , s. 57-59
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
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| 10. |
- Hemani, Ahmed, et al.
(författare)
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High-level synthesis of control and memory intensive communication systems
- 1995
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Ingår i: ; , s. 185-191
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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| 11. |
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| 12. |
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| 13. |
- Horn, Wolfgang, et al.
(författare)
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Hardware synthesis of an ATM multiplexer from SDL to VHDL : a case study
- 1999
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Ingår i: VLSI ’99. Proceedings IEEE Computer Society Workshop On. ; , s. 100-105
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Konferensbidrag (refereegranskat)abstract
- Hardware synthesis of SDL models poses several problems, because SDL uses Communicating Sequential Processes (CSP) paradigm for system specification. It allows dynamic processes and its semantics assume an infinite FIFO buffer at the input of each process for inter-process communication. We had presented previously a methodology and later refined it for efficient hardware synthesis from SDL specification. In this paper we describe the experience of applying this methodology to a large case study. The case study is an ATM Multiplexer which exhibits a complex control flow and uses large tables. It was modelled using multiple processes. Hardware synthesis was carried out using the methodology starting from its SDL model. The results show that the methodology leads to a correct and efficient hardware implementation. In particular, the methodology avoids use of costly FIFO buffers for implementing inter-process communication and allows sharing of hardware resources among various instances of the same process. The final implementation also meets the 155 Mbit/sec data rate performance requirement
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| 14. |
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| 15. |
- Jafri, Syed Mohammad Asad Hassan, et al.
(författare)
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Self-Adaptive NoC Power Management with Dual-Level Agents : Architecture and Implementation
- 2012
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Ingår i: PECCS 2012 - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems. - 9789898565006 ; , s. 450-458
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Konferensbidrag (refereegranskat)abstract
- Architecture and Implementation of adaptive NoC to improve performance and power consumption is presented. On platforms hosting multiple applications, hardware variations and unpredictable workloads make static design-time assignments highly sub-optimal e.g. in terms of power and performance. As a solution to this problem, adaptive NoCs are designed, which dynamically adapt towards optimal implementation. This paper addresses the architectural design of adaptive NoC, which is an essential step towards design automation. The architecture involves two levels of agents: a system level agent implemented in software on a dedicated general purpose processor and the local agents implemented as microcontrollers of each network node. The system agent issues specific instructions to perform monitoring and reconfiguration operations, while the local agents operate according to the commands from the system agent. To demonstrate the system architecture, best-effort power management with distributed voltage and frequency scaling is implemented, while meeting run-time execution requirements. Four benchmarks (matrix multiplication, FFT, wavefront, and hiperLAN transmitter) are experimented on a cycle-accurate RTL-level shared-memory NoC simulator. Power analysis with 65nm multi-Vdd library shows a significant reduction in energy consumption (from 21 % to 36 %). The synthesis also shows minimal area overhead (4 %) of the local agent compared to the original NoC switch.
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| 16. |
- Jantsch, Axel, et al.
(författare)
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A Case Study on Hardware/Software Partitioning
- 1994
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Ingår i: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines. - : IEEE conference proceedings. - 0818654902 ; , s. 111-118
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Konferensbidrag (refereegranskat)abstract
- We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.
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| 17. |
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| 18. |
- Jantsch, Axel, et al.
(författare)
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A metamodel for studying concepts in electronic system design
- 2000
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Ingår i: IEEE Design & Test of Computers. - : IEEE Press. - 0740-7475 .- 1558-1918. ; 17:3, s. 78-85
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Tidskriftsartikel (refereegranskat)abstract
- By using the four domains of computation, data, communication, and time, this model can represent mixed hardware/software designs and related co-design processes at various levels of abstraction.
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| 19. |
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| 20. |
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| 21. |
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| 22. |
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| 23. |
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| 24. |
- Jantsch, Axel, et al.
(författare)
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The Rugby Model : a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems
- 1999
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Ingår i: Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings. ; , s. 256-262
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Konferensbidrag (refereegranskat)abstract
- We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimensions for design representation, namely Data and Tune. The behavioural domain of Y chart is replaced by a more restricted domain called Computation. The structural and physical domains of Y chart are merged into a more general domain called Communication. A fifth dimension deals with design manipulations and transformations at three abstraction levels. The model shall establish a common understanding of modelling and design process concepts for communication and education in the community. In a case study we illustrate how a design can be characterized with the concepts the Rugby model
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| 25. |
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| 26. |
- Kumar, Shashi, et al.
(författare)
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A network on chip architecture and design methodology
- 2002
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Ingår i: VLSI 2002. - : IEEE conference proceedings. - 0769514863 ; , s. 105-112
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Konferensbidrag (refereegranskat)abstract
- We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
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| 27. |
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| 28. |
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| 29. |
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| 30. |
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| 31. |
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| 32. |
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| 33. |
- O'Nils, Mattias, et al.
(författare)
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Design of D-AMPS Channel Decoder with Codesign Methodologies
- 1996
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Ingår i: BEC '96, the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings. - Tallinn, Estonia : Tallinn Technical University. - 9789985590263 ; , s. 491-
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Konferensbidrag (refereegranskat)abstract
- This paper is a case study on tool based codesign methodology. The presented methods are observed by applying a D-AMPS channel decoder design to a codesign research tool-kit. The channel decoder functionality is described with five thousand lines of C code. The analysis (profiling, estimation, hardware-software partitioning and verification) of the C description are presented in the paper.
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| 34. |
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| 35. |
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| 36. |
- Svantesson, Bengt, et al.
(författare)
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A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts
- 1996
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: Characterise CMISTs from the synthesis viewpoint; Contend that the synthesis demands of CMISTs can be met within the framework of a general purpose High-level synthesis tool, by making parts of it adaptive to the input, rather than develop a complete tool for a particular type of application; Present an allocation strategy that automatically adapts for CMISTs; Present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; Present the results of applying the synthesis methodology to the OAM as a test case. The results are compared with the result from two commercial High-level synthesis tool; Prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our obtained by designing manually at register-transfer level; The results is also compared with the results from two commercial HLS tools.
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| 37. |
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| 38. |
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| 39. |
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| 40. |
- Tammemäe, Kalle, et al.
(författare)
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AKKA: A Tool-kit for Cosynthesis and Prototyping
- 1996
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Ingår i: Hardware-Software Cosynthesis for Reconfigurable Systems, IEE Colloquium, Bristol 22 Feb. 1996. - : IEE. ; , s. 8/1-8/8
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Shortened design and life time of embedded systems has motivated active research in HW/SW co-design area, together with evolution of relatively long-life of reconfigurable HW. In this paper we present Akka1[1][2] - a set of tools for design space exploration, co-simulation and co-synthesis with two industrial examples from the telecommunication field - Maintenance functionality of the ATM protocol and Channel decoder functionality of a D-AMPS base station. For fast prototyping we have selected Xilinx XC4013 FPGA based board from Virtual Computer Corporation. The board is connected to the system bus (SBus) of the host computer.
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| 41. |
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| 42. |
- Öberg, Johnny, et al.
(författare)
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A rule-based approach for improving allocation of filter structures in HLS
- 1996
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Ingår i: Ninth International Conference on VLSI Design, 1996. Proceedings. - : IEEE conference proceedings. - 0818672285 ; , s. 133-139
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Konferensbidrag (refereegranskat)abstract
- A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool
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| 43. |
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| 44. |
- Öberg, Johnny, et al.
(författare)
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Grammar-based design of embedded systems
- 2001
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Ingår i: Journal of systems architecture. - : Elsevier. - 1383-7621 .- 1873-6165. ; 47:3-4, s. 225-240
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Tidskriftsartikel (refereegranskat)abstract
- Grammars define syntax of languages and as such have not been commonly considered as methods for design, despite well-known applications in computer science. Only in recent years grammar-based design has become a promising research field and the first commercial tools have appeared on the market. This paper reviews the basic concepts of applying grammars to electronic design - in particular to the device driver synthesis of communication protocols for embedded software, to the design of custom-hardware, and to the virtual prototyping of DSP systems. The paper shows the power of these methods, presents the latest research results and discusses future developments in this field.
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