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  • Candaele, Bernard (author)

Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach

  • Article/chapterEnglish2010

Publisher, publication year, extent ...

  • 2010
  • printrdacarrier

Numbers

  • LIBRIS-ID:oai:DiVA.org:kth-63629
  • https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-63629URI
  • https://doi.org/10.1109/ISVLSI.2010.71DOI

Supplementary language notes

  • Language:English
  • Summary in:English

Part of subdatabase

Classification

  • Subject category:ref swepub-contenttype
  • Subject category:kon swepub-publicationtype

Notes

  • QC 20120201
  • The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

Subject headings and genre

Added entries (persons, corporate bodies, meetings, titles ...)

  • Aguirre, Sylvain (author)
  • Sarlotte, Michel (author)
  • Anagnostopoulos, Iraklis (author)
  • Xydis, Sotirios (author)
  • Bartzas, Alexandros (author)
  • Bekiaris, Dimitris (author)
  • Soudris, Dimitrios (author)
  • Lu, ZhonghaiKTH,Elektroniksystem(Swepub:kth)u1wqy6h0 (author)
  • Chen, XiaowenKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1a3w6t8 (author)
  • Chabloz, Jean-MichelKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u1ao3un8 (author)
  • Hemani, AhmedKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u131a9ju (author)
  • Jantsch, AxelKTH,Elektronik- och datorsystem, ECS(Swepub:kth)u18wycaf (author)
  • Vanmeerbeeck, Geert (author)
  • Kreku, Jari (author)
  • Tiensyrja, Kari (author)
  • Ieromnimon, Fragkiskos (author)
  • Kritharidis, Dimitrios (author)
  • Wiefrink, Andreas (author)
  • Vanthournout, Bart (author)
  • Martin, Philippe (author)
  • KTHElektroniksystem (creator_code:org_t)

Related titles

  • In:Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, s. 518-5239780769540764

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