Sökning: onr:"swepub:oai:lup.lub.lu.se:8e361bcb-08c1-4180-baf5-8269eb013e34" >
A High-Speed QR Dec...
A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems
-
- Gangarajaiah, Rakesh (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
-
- Liu, Liang (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
-
- Stala, Michal (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
-
visa fler...
-
- Nilsson, Peter (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
-
- Edfors, Ove (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
-
visa färre...
-
(creator_code:org_t)
- 2013
- 2013
- Engelska 4 s.
- Relaterad länk:
-
https://portal.resea... (primary) (free)
-
visa fler...
-
https://lup.lub.lu.s...
-
visa färre...
Abstract
Ämnesord
Stäng
- This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publikations- och innehållstyp
- kon (ämneskategori)
- ref (ämneskategori)