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Leakage-Conscious A...
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
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- Do, Minh Quang, 1969 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Drazdziulis, Mindaugas, 1978 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Larsson-Edefors, Per, 1967 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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visa fler...
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- Bengtsson, Lars, 1958 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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visa färre...
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(creator_code:org_t)
- 2007
- 2007
- Engelska.
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Ingår i: 8th International Symposium on Quality Electronic Design (ISQED’07). ; , s. 185 - 191
- Relaterad länk:
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https://research.cha...
Abstract
Ämnesord
Stäng
- We propose a methodology and power models for an accuratehigh-level power estimation of physically partitionedand power-gated SRAM arrays. The models offer accurateestimation of both dynamic and leakage power, includingthe power dissipation due to emerging leakage mechanismssuch as gate oxide tunneling, for partitioned arrays that deploydata-retaining sleep techniques for leakage reduction.Using the proposed methodology, dynamic, leakage and totalpower of partitioned SRAM arrays can be estimated witha 97% accuracy in comparison to the power obtained byrunning full circuit-level simulations.
Ämnesord
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Nyckelord
- Deep Submicron
- SRAM Power Modeling
- VLSI
- CMOS
- Power Estimation
Publikations- och innehållstyp
- kon (ämneskategori)
- ref (ämneskategori)